Renesas R61509V Manuel D’Utilisation
R61509V
Target
Spec
Rev. 0.11 April 25, 2008, page 11 of 181
Block Function
1. System
Interface
The R61509V supports 80-system high-speed interface via 8-, 9-, 16-, 18-bit parallel ports and a clock
synchronous serial interface. The interface is selected by setting the IM2-0 pins.
synchronous serial interface. The interface is selected by setting the IM2-0 pins.
The R61509V has 16-bit index register (IR), 18-bit write-data register (WDR), and 18-bit read-data register
(RDR). The IR is the register to store index information from control register and internal GRAM. The
WDR is the register to temporarily store write data to control register and internal GRAM. The RDR is the
register to temporarily store the read data from the GRAM. The write data from the host processor to the
internal GRAM is first written to the WDR and then automatically written to the internal GRAM by
internal operation. The data is read via RDR from the internal GRAM. Therefore, invalid data is sent to
the data bus when the R61509V performs the first read operation from the internal GRAM. Valid data is
read out when the R61509V performs the second and subsequent read operation.
(RDR). The IR is the register to store index information from control register and internal GRAM. The
WDR is the register to temporarily store write data to control register and internal GRAM. The RDR is the
register to temporarily store the read data from the GRAM. The write data from the host processor to the
internal GRAM is first written to the WDR and then automatically written to the internal GRAM by
internal operation. The data is read via RDR from the internal GRAM. Therefore, invalid data is sent to
the data bus when the R61509V performs the first read operation from the internal GRAM. Valid data is
read out when the R61509V performs the second and subsequent read operation.
The R61509V allows writing instructions consecutively by executing the instruction in the same cycle
when it is written (0 instruction cycle).
when it is written (0 instruction cycle).
Table 2 Register Selection (80-System 8-/9-/16-/18-Bit Parallel Interface)
WRX RDX
RS
Function
0
1
0
Write index to IR
1 0 0
Setting
disabled
0
1
1
Write to control register or internal GRAM via WDR
1
0
1
Read from internal GRAM and register via RDR
Table 3 Register Selection (Clock Synchronous Serial Interface)
Start byte
R/W RS
Function
0
0
Write index to IR
1 0 Setting
disabled
0
1
Write to control register or internal GRAM via WDR
1
1
Read from internal GRAM and register via RDR