Renesas R61509V Manuel D’Utilisation

●R61509V　Instruction List

Rev 0.50 2008. 04. 22

Middle category

Upper Index

Index

Command

IB15

IB14

IB13

IB12

IB11

IB10

IB9

IB8

IB7

IB6

IB5

IB4

IB3

IB2

IB1

IB0

Index

－

Index

ID10

ID9

ID8

ID7

ID6

ID5

ID4

ID3

ID2

ID21

ID0

0**

Display Control

00*

000h

Device Code Read

ALMID1[7]

(1)

ALMID1[6]

(0)

ALMID1[5]

(1)

ALMID1[4]

(1)

ALMID1[3]

(0)

ALMID1[2]

(1)

ALMID1[1]

(0)

ALMID1[0]

(1)

ALMID0[7]

(0)

ALMID0[6]

(0)

ALMID0[5]

(0)

ALMID0[4]

(0)

ALMID0[3]

(1)

ALMID0[2]

(0)

ALMID0[1]

(0)

ALMID0[0]

(1)

Display Control

in general

001h

Driver Output Control

(0)

002h

LCD Drive Waveform Control

(0)

003h

Entry Mode

TRI

(0)

DFM

(0)

BGR

(0)

ORG

(0)

ID[1]

(1)

ID[0]

(1)

(0)

004h

Setting inhibited

005h

Setting inhibited

006h

Setting inhibited

007h

Display Control 1

PTDE

(0)

BASEE

(0)

008h

Display Control 2

FP[7]

(0)

FP[6]

(0)

FP[5]

(0)

FP[4]

(0)

FP[3]

(1)

FP[2]

(0)

FP[1]

(0)

FP[0]

(0)

BP[7]

(0)

BP[6]

(0)

BP[5]

(0)

BP[4]

(0)

BP[3]

(1)

BP[2]

(0)

BP[1]

(0)

BP[0]

(0)

009h

Display Control 3

PTV

(0)

PTS

(0)

00Ah

Setting inhibited

00Bh

8 Color Control

COL

(0)

00Ch

External Display Interface Control

ENC[2]

(0)

ENC[1]

(0)

ENC[0]

(0)

DM[1]

(0)

DM[0]

(0)

RIM

(0)

00D-00Eh

Setting inhibited

00Fh

External Display Interface Control

VSPL

(0)

HSPL

(0)

EPL

(0)

DPL

(0)

01*

010h

Panel Interface Control 1

DIVI[1]

(0)

DIVI[0]

(0)

RTNI[4]

(1)

RTNI[3]

(1)

RTNI[2]

(0)

RTNI[1]

(0)

RTNI[0]

(1)

Panel Interface
(Internal Clock)

011h

Panel Interface Control 2

NOWI[2]

(0)

NOWI[1]

(0)

NOWI[0]

(1)

SDTI[2]

(0)

SDTI[1]

(0)

SDTI[0]

(1)

012h

Panel Interface Control 3

VEQWI[2]

(0)

VEQWI[1]

(0)

VEQWI[0]

(0)

SEQWI[2]

(0)

SEQWI[1]

(0)

SEQWI[0]

(0)

013h

Panel Interface Control 4

MCPI[2]

(0)

MCPI[1]

(0)

MCPI[0]

(1)

014h

Panel Interface Control 5

PCDIVH[2]

(1)

PCDIVH[1]

(0)

PCDIVH[0]

(1)

PCDIVL[2]

(1)

PCDIVL[1]

(0)

PCDIVL[0]

(1)

014-01Fh

Setting inhibited

02*

020h

Panel Interface Control 6

DIVE[1]

(0)

DIVE[0]

(0)

RTNE[4]

(1)

RTNE[3]

(1)

RTNE[2]

(0)

RTNE[1]

(0)

RTNE[0]

(1)

Panel Interface

(External Clock)

021h

Panel Interface Control 7

NOWE[2]

(0)

NOWE[1]

(0)

NOWE[0]

(1)

SDTE[2]

(0)

SDTE[1]

(0)

SDTE[0]

(1)

022h

Panel Interface Control 8

VEQWE[2]

(0)

VEQWE[1]

(0)

VEQWE[0]

(0)

SEQWE[2]

(0)

SEQWE[1]

(0)

SEQWE[0]

(0)

023h

Panel Interface Control 9

MCPE[2]

(0)

MCPE[1]

(0)

MCPE[0]

(1)

024h-08Fh

Setting inhibited

09*

090h

Frame Marker Control

FMKM

(0)

FMI[2]

(0)

FMI[1]

(0)

FMI[0]

(0)

FMP[8]

(0)

FMP[7]

(0)

FMP[6]

(0)

FMP[5]

(0)

FMP[4]

(0)

FMP[3]

(0)

FMP[2]

(0)

FMP[1]

(0)

FMP[0]

(0)

Frame Marker Control 091-0FFh

Setting inhibited

1**

Power Control

100h

Power Control 1

BT[2]

(0)

BT[1]

(1)

BT[0]

(1)

AP[1]

(1)

AP[0]

(1)

DSTB

(0)

101h

Power Control 2

DC1[2]

(0)

DC1[1]

(1)

DC1[0]

(0)

DC0[2]

(1)

DC0[1]

(0)

DC0[0]

(0)

VC[2]

(1)

VC[1]

(1)

VC[0]

(1)

102h

Power Control 3

VRH[4]

(0)

VRH[3]

(0)

VRH[2]

(0)

VRH[1]

(0)

VRH[0]

(0)

VCMR

(1)

PSON

(0)

PON

(0)

103h

Power Control 4

VDV[4]

(0)

VDV[3]

(0)

VDV[2]

(0)

VDV[1]

(0)

VDV[0]

(0)

104-1FFh

Setting inhibited

2**

RAM Access

20*

200h

RAM Address Set

(Horizontal Address)

AD[7]

(0)

AD[6]

(0)

AD[5]

(0)

AD[4]

(0)

AD[3]

(0)

AD[2]

(0)

AD[1]

(0)

AD[0]

(0)

RAM Read/Write

201h

RAM Address Set

(Vertical Address)

AD[16]

(0)

AD[15]

(0)

AD[14]

(0)

AD[13]

(0)

AD[12]

(0)

AD[11]

(0)

AD[10]

(0)

AD[9]

(0)

AD[8]

(0)

202h

GRAM Data Write/GRAM Data

Read

203-20Fh

Setting inhibited

21*

210h

Window Horizontal RAM Address

Start

HSA[7]

(0)

HSA[6]

(0)

HSA[5]

(0)

HSA[4]

(0)

HSA[3]

(0)

HSA[2]

(0)

HSA[1]

(0)

HSA[0]

(0)

Window Address

211h

Window Horizontal RAM Address

End

HEA[7]

(1)

HEA[6]

(1)

HEA[5]

(1)

HEA[4]

(0)

HEA[3]

(1)

HEA[2]

(1)

HEA[1]

(1)

HEA[0]

(1)

212h

Window Vertical RAM Address

Start

VSA[8]

(0)

VSA[7]

(0)

VSA[6]

(0)

VSA[5]

(0)

VSA[4]

(0)

VSA[3]

(0)

VSA[2]

(0)

VSA[1]

(0)

VSA[0]

(0)

213h

Window Vertical RAM Address End

VEA[8]

(1)

VEA[7]

(1)

VEA[6]

(0)

VEA[5]

(1)

VEA[4]

(0)

VEA[3]

(1)

VEA[2]

(1)

VEA[1]

(1)

VEA[0]

(1)

214-27Fh

Setting inhibited

28*

280h

NVM Data Read / NVM Data Write

VCM[6]

(1)

VCM[5]

(1)

VCM[4]

(1)

VCM[3]

(1)

VCM[2]

(1)

VCM[1]

(1)

VCM[0]

(1)

UID[7]

(1)

UID[6]

(1)

UID[5]

(1)

UID[4]

(1)

UID[3]

(1)

UID[2]

(1)

UID[1]

(1)

UID[0]

(1)

281-2FFh

Setting inhibited

3**

Gamma Control

30*

300h

Gamma Control (1)

PR0P01[4]

(0)

PR0P01[3]

(0)

PR0P01[2]

(0)

PR0P01[1]

(0)

PR0P01[0]

(0)

PR0P00[4]

(0)

PR0P00[3]

(0)

PR0P00[2]

(0)

PR0P00[1]

(0)

PR0P00[0]

(0)

Gamma Control

301h

Gamma Control (2)

PR0P04[3]

(0)

PR0P04[2]

(0)

PR0P04[1]

(0)

PR0P04[0]

(0)

PR0P03[3]

(0)

PR0P03[2]

(0)

PR0P03[1]

(0)

PR0P03[0]

(0)

PR0P02[4]

(0)

PR0P02[3]

(0)

PR0P02[2]

(0)

PR0P02[1]

(0)

PR0P02[0]

(0)

302h

Gamma Control (3)

PR0P06[4]

(0)

PR0P06[3]

(0)

PR0P06[2]

(0)

PR0P06[1]

(0)

PR0P06[0]

(0)

PR0P05[3]

(0)

PR0P05[2]

(0)

PR0P05[1]

(0)

PR0P05[0]

(0)

303h

Gamma Control (4)

PR0P08[4]

(0)

PR0P08[3]

(0)

PR0P08[2]

(0)

PR0P08[1]

(0)

PR0P08[0]

(0)

PR0P07[4]

(0)

PR0P07[3]

(0)

PR0P07[2]

(0)

PR0P07[1]

(0)

PR0P07[0]

(0)

304h

Gamma Control (5)

PI0P3[1]

(0)

PI0P3[0]

(0)

PI0P2[1]

(0)

PI0P2[0]

(0)

PI0P1[1]

(0)

PI0P1[0]

(0)

PI0P0[1]

(0)

PI0P0[0]

(0)

305h

Gamma Control (6)

PR0N01[4]

(0)

PR0N01[3]

(0)

PR0N01[2]

(0)

PR0N01[1]

(0)

PR0N01[0]

(0)

PR0N00[4]

(0)

PR0N00[3]

(0)

PR0N00[2]

(0)

PR0N00[1]

(0)

PR0N00[0]

(0)

306h

Gamma Control (7)

PR0N04[3]

(0)

PR0N04[2]

(0)

PR0N04[1]

(0)

PR0N04[0]

(0)

PR0N03[3]

(0)

PR0N03[2]

(0)

PR0N03[1]

(0)

PR0N03[0]

(0)

PR0N02[4]

(0)

PR0N02[3]

(0)

PR0N02[2]

(0)

PR0N02[1]

(0)

PR0N02[0]

(0)

307h

Gamma Control (8)

PR0N06[4]

(0)

PR0N06[3]

(0)

PR0N06[2]

(0)

PR0N06[1]

(0)

PR0N06[0]

(0)

PR0N05[3]

(0)

PR0N05[2]

(0)

PR0N05[1]

(0)

PR0N05[0]

(0)

308h

Gamma Control (9)

PR0N08[4]

(0)

PR0N08[3]

(0)

PR0N08[2]

(0)

PR0N08[1]

(0)

PR0N08[0]

(0)

PR0N07[4]

(0)

PR0N07[3]

(0)

PR0N07[2]

(0)

PR0N07[1]

(0)

PR0N07[0]

(0)

309h

Gamma Control (10)

PI0N3[1]

(0)

PI0N3[0]

(0)

PI0N2[1]

(0)

PI0N2[0]

(0)

PI0N1[1]

(0)

PI0N1[0]

(0)

PI0N0[1]

(0)

PI0N0[0]

(0)

30Ah-3FFh

Setting inhibited

4**

400ｈ

Base Image Number of Line

(0)

NL[5]

(1)

NL[4]

(1)

NL[3]

(0)

NL[2]

(1)

NL[1]

(0)

NL[0]

(1)

SCN[5]

(0)

SCN[4]

(0)

SCN[3]

(0)

SCN[2]

(0)

SCN[1]

(0)

SCN[0]

(0)

401h

Base Image Display Control

NDL

(0)

VLE

(0)

REV

(0)

402h-403h

Setting inhibited

404h

Base Image Vertical Scroll Control

VL[8]

(0)

VL[7]

(0)

VL[6]

(0)

VL[5]

(0)

VL[4]

(0)

VL[3]

(0)

VL[2]

(0)

VL[1]

(0)

VL[0]

(0)

405-4FFh

Setting inhibited

5**

500h

Partial Image 1: Display Position

PTDP[8]

(0)

PTDP[7]

(0)

PTDP[6]

(0)

PTDP[5]

(0)

PTDP[4]

(0)

PTDP[3]

(0)

PTDP[2]

(0)

PTDP[1]

(0)

PTDP[0]

(0)

501h

RAM Address 1 (Start Line

Address)

PTSA[8]

(0)

PTSA[7]

(0)

PTSA[6]

(0)

PTSA[5]

(0)

PTSA[4]

(0)

PTSA[3]

(0)

PTSA[2]

(0)

PTSA[1]

(0)

PTSA[0]

(0)

502h

RAM Address 2 (End Line Address)

PTEA[8]

(0)

PTEA[7]

(0)

PTEA[6]

(0)

PTEA[5]

(0)

PTEA[4]

(0)

PTEA[3]

(0)

PTEA[2]

(0)

PTEA[1]

(0)

PTEA[0]

(0)

503h-5FFh

Setting inhibited

6**

Pin Control

60*

600h

Test Register (Software Reset)

TRSR

(0)

601-6EFh

Setting inhibited

6F*

6F0h

NVM Access Control 1

TE
(0)

CALB

(0)

EOP[1]

(0)

EOP[0]

(0)

6F1h

NVM Access Control 2

NVDAT[15]

(0)

NVDAT[14]

(0)

NVDAT[13]

(0)

NVDAT[12]

(0)

NVDAT[11]

(0)

NVDAT[10]

(0)

NVDAT[9]

(0)

NVDAT[8]

(0)

NVDAT[7]

(0)

NVDAT[6]

(0)

NVDAT[5]

(0)

NVDAT[4]

(0)

NVDAT[3]

(0)

NVDAT[2]

(0)

NVDAT[1]

(0)

NVDAT[0]

(0)

6F2h

NVM Access Control 3

NVVRF

(0)

NVM-I/F

6F3-FFFh

Setting inhibited

Note 1: Values in parentheses ( ) are default values.
Note 2: Do not access instructions that are not shown in the above table.

Base Image Display Control

Partial Display Control

RAM write data WD[17:0] / RAM read data RD [17:0] is transferred via different data bus in different interface operation.

Major category

Minor category

Upper Code

Lower Code

Note

Device Code

"B509h"