Philips 8-bit microcontroller with two-clock 80C51 core UM10109 Manuel D’Utilisation

 

© Koninklijke Philips Electronics N.V. 2005. All rights reserved.

When the timer changes direction at the bottom, in this example, it counts …,0001H, 
0000H, 0001H,… The CCU Timer overflow interrupt flag is set in the counter CCUCLK 
cycle after the transition from 0001H to 0000H.

The status of the TDIR2 bit in TCR20 reflects the current counting direction. Writing to this 
bit while operating in symmetrical mode has no effect.

In asymmetrical mode, the user can program PWM channels A/B and C/D as alternating 
pairs for bridge drive control. By setting ALTAB or ALTCD bits in TCR20, the output of 
these PWM channels are alternately gated on every counter cycle. This is shown in the 
following figure:

[1]

x = A, B, C, D

[2]

‘ON’ means in the CCUCLK cycle after the event takes place.

0

0

Output compare disabled. On power-on, this is the default state, and pins 
are configured as inputs.

0

1

Set when compare in 
operation. Cleared on 
compare match.

Non-Inverted PWM. Set 
on compare match. 
Cleared on CCU Timer 
underflow.

Non-Inverted PWM. 
Cleared on compare 
match, upcounting. Set 
on compare match, 
downcounting.

1

0

invalid configuration

1

1

Toggles on compare 
match

Inverted PWM. Cleared 
on compare match. Set 
on CCU Timer 
underflow.

Inverted PWM. Set on 
compare match, 
upcounting. Cleared on 
compare match, 
downcounting.

TIMER VALUE

002aaa895

0

TOR2

COMPARE VALUE A (or C)

COMPARE VALUE B (or D)

PWM OUTPUT A (or C)   (P2.6)

PWM OUTPUT B (or D)   (P1.6)