New Transducers TR-5001 Manuel D’Utilisation

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Advanced Chipset Features 
 
Phoenix – AwardBIOS CMOS Setup Utility 
Advanced Chipset Features 
DRAM Timing Selectable                        [By SPD] 
x CAS Latency Time                                  [2.5] 
x Active to Precharge Delay                   
[6] 
x DRAM RAS# to CAS# Delay              
[3] 
x DRAM RAS# Precharge                           [3] 
Memory Frequency For                             [Auto] 
System BIOS Cacheable                        [Enabled] 
Video BIOS Cacheable 
                      [Disabled] 
Memory Hole At 15M-16M                       [Disabled] 
AGP Aperture Size (MB)                        [128] 
Init Display First                                       [PCI Slot] 
 
***On-Chip VGA Setting*** 
    On-Chip VGA                                        [Enabled] 
    On-Chip Frame Buffer Size 
              [8MB] 
    Boot Display 
                                      [Auto] 
    Panel Number                                        [Auto] 
      Item Help 
 
Menu Level      ¾ 
 
 
↑↓←→
Move Enter: Select +/-/PU/PD: Value F10:Save ESC: Exit F1:General Help 
    F5:Previous Values     F6:Fail-safe defaults      F7:Optimized Defaults 
 
This section allows you to configure the system based on the specific 
features of the installed chipset. This chipset manages bus speeds and 
access to system memory resources, such as DRAM and the external 
cache.  It also coordinates communications between the conventional 
ISA bus and the PCI bus. It must be stated that these items should never 
need to be altered. The default settings have been chosen because they 
provide the best operating conditions for your system. The only time 
you might consider making any changes would be if you discovered 
that data was being lost while using your system. 
DRAM Settings 
The first chipset settings deal with CPU access to dynamic random 
access memory (DRAM).  The default timings have been carefully 
chosen and should only be altered if data is being lost.  Such a scenario 
might well occur if your system had mixed speed DRAM chips 
installed so that greater delays may be required to preserve the integrity 
of the data held in the slower memory chips. 
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TR-5001 User Manual