LSI 53C875A Manuel D’Utilisation
64-Bit SCRIPTS Selectors
4-101
Registers: 0xA4–0xA7
Memory Move Write Selector (MMWS)
Read/Write
Read/Write
MMWS
Memory Move Write Selector
[31:0]
Supplies the upper Dword of a 64-bit address during data
write operations during Memory-to-Memory Moves and
absolute address STORE operations.
write operations during Memory-to-Memory Moves and
absolute address STORE operations.
A special mode of this register can be enabled by setting
the PCI Configuration Into Enable bit in the
the PCI Configuration Into Enable bit in the
register. Because the LSI53C875A supports
only a 32-bit SCRIPTS RAM PCI base address, the
MMWS register is always read as 0x00000000 when in
the special mode.
MMWS register is always read as 0x00000000 when in
the special mode.
Writes to the MMWS register are unaffected. Clearing the
PCI Configuration Enable bit causes the MMWS register
to return to normal operation.
PCI Configuration Enable bit causes the MMWS register
to return to normal operation.
Registers: 0xA8–0xAB
SCRIPTS Fetch Selector (SFS)
Read/Write
Read/Write
SFS
SCRIPTS Fetch Selector
[31:0]
Supplies the upper Dword of a 64-bit address during
SCRIPTS fetches and Indirect fetches (excluding Table
Indirect fetches). This register can be loaded
automatically using a 64-bit jump instruction.
SCRIPTS fetches and Indirect fetches (excluding Table
Indirect fetches). This register can be loaded
automatically using a 64-bit jump instruction.
A special mode of this register can be enabled by setting
the PCI Configuration Into Enable bit in the
the PCI Configuration Into Enable bit in the
register. If this bit is set, bits [23:16] of the SFS
register return the PCI
register value
and bits [15:0] return the PCI
register value
when read.
31
0
MMWS
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
31
0
SFS
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0