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Intel Xeon E5502
Manuel D’Utilisation
IBM Intel Xeon E5502 46D1350 Manuel D’Utilisation
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46D1350
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Intel® Xeon® Processor 5500 Series Datasheet, Volume 2
5
2.11.10 MC_SCRUBADDR_LO............................................................................. 79
2.11.11 MC_SCRUBADDR_HI ............................................................................. 79
2.12 TAD - Target Address Decoder Registers .............................................................. 80
2.12.1
TAD_DRAM_RULE_0
TAD_DRAM_RULE_1
TAD_DRAM_RULE_2
TAD_DRAM_RULE_3
TAD_DRAM_RULE_4
TAD_DRAM_RULE_5
TAD_DRAM_RULE_6
TAD_DRAM_RULE_7.............................................................................. 80
2.12.2
TAD_INTERLEAVE_LIST_0
TAD_INTERLEAVE_LIST_1
TAD_INTERLEAVE_LIST_2
TAD_INTERLEAVE_LIST_3
TAD_INTERLEAVE_LIST_4
TAD_INTERLEAVE_LIST_5
TAD_INTERLEAVE_LIST_6
TAD_INTERLEAVE_LIST_7...................................................................... 81
2.13 Integrated Memory Controller RAS Registers......................................................... 82
2.13.1
MC_SSRCONTROL................................................................................. 82
2.13.2
MC_SCRUB_CONTROL ........................................................................... 83
2.13.3
MC_RAS_ENABLES................................................................................ 83
2.13.4
MC_RAS_STATUS ................................................................................. 83
2.13.5
MC_SSRSTATUS ................................................................................... 84
2.13.6
MC_COR_ECC_CNT_0
MC_COR_ECC_CNT_1
MC_COR_ECC_CNT_2
MC_COR_ECC_CNT_3
MC_COR_ECC_CNT_4
MC_COR_ECC_CNT_5............................................................................ 84
2.14 Integrated Memory Controller Test Registers......................................................... 85
2.14.1
MC_TEST_ERR_RCV1 ............................................................................ 85
2.14.2
MC_TEST_ERR_RCV0 ............................................................................ 85
2.14.3
MC_TEST_PH_CTR ................................................................................ 86
2.14.4
MC_TEST_PH_PIS ................................................................................. 86
2.14.5
MC_TEST_PAT_GCTR ............................................................................ 86
2.14.6
MC_TEST_PAT_BA ................................................................................ 87
2.14.7
MC_TEST_PAT_IS ................................................................................. 87
2.14.8
MC_TEST_PAT_DCD .............................................................................. 87
2.15 Integrated Memory Controller Channel Control Registers ........................................ 88
2.15.1
MC_CHANNEL_0_DIMM_RESET_CMD
MC_CHANNEL_1_DIMM_RESET_CMD
MC_CHANNEL_2_DIMM_RESET_CMD....................................................... 88
2.15.2
MC_CHANNEL_0_DIMM_INIT_CMD
MC_CHANNEL_1_DIMM_INIT_CMD
MC_CHANNEL_2_DIMM_INIT_CMD.......................................................... 88
2.15.3
MC_CHANNEL_0_DIMM_INIT_PARAMS
MC_CHANNEL_1_DIMM_INIT_PARAMS
MC_CHANNEL_2_DIMM_INIT_PARAMS .................................................... 89
2.15.4
MC_CHANNEL_0_DIMM_INIT_STATUS
MC_CHANNEL_1_DIMM_INIT_STATUS
MC_CHANNEL_2_DIMM_INIT_STATUS ..................................................... 91
2.15.5
MC_CHANNEL_0_DDR3CMD
MC_CHANNEL_1_DDR3CMD
MC_CHANNEL_2_DDR3CMD ................................................................... 92
2.15.6
MC_CHANNEL_0_REFRESH_THROTTLE_SUPPORT
MC_CHANNEL_1_REFRESH_THROTTLE_SUPPORT
MC_CHANNEL_2_REFRESH_THROTTLE_SUPPORT...................................... 93
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