Intel E5530 AT80602000792AA Manuel D’Utilisation
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Codes de produits
AT80602000792AA
Thermal Specifications
108
Intel
®
Xeon
®
Processor 5500 Series Datasheet, Volume 1
Note:
1.
Refer to
for a summary of mailbox commands supported by the Intel Xeon processor 5500
series CPU.
6.3.1
PECI Client Capabilities
The Intel Xeon processor 5500 series PECI client is designed to support the following
sideband functions:
sideband functions:
• Processor and DRAM thermal management
• Platform manageability functions including thermal, power and electrical error
• Platform manageability functions including thermal, power and electrical error
monitoring
• Processor interface tuning and diagnostics capabilities (Intel
®
Interconnect BIST
(Intel
®
IBIST)).
6.3.1.1
Thermal Management
Processor fan speed control is managed by comparing PECI thermal readings against
the processor-specific fan speed control reference point, or T
the processor-specific fan speed control reference point, or T
CONTROL
. Both T
CONTROL
and PECI thermal readings are accessible via the processor PECI client. These variables
are referenced to a common temperature, the TCC activation point, and are both
defined as negative offsets from that reference. Algorithms for fan speed management
using PECI thermal readings and the T
are referenced to a common temperature, the TCC activation point, and are both
defined as negative offsets from that reference. Algorithms for fan speed management
using PECI thermal readings and the T
CONTROL
reference are documented in
PECI-based access to DRAM thermal readings and throttling control coefficients provide
a means for Board Management Controllers (BMCs) or other platform management
devices to feed hints into on-die memory controller throttling algorithms. These control
coefficients are accessible using PCI configuration space writes via PECI. The PECI-
based configuration write functionality is defined in
a means for Board Management Controllers (BMCs) or other platform management
devices to feed hints into on-die memory controller throttling algorithms. These control
coefficients are accessible using PCI configuration space writes via PECI. The PECI-
based configuration write functionality is defined in
, and the DRAM
throttling coefficient control functions are documented in the Intel® Xeon® Processor
5500 Series Datasheet, Volume 2.
5500 Series Datasheet, Volume 2.
6.3.1.2
Platform Manageability
PECI allows full read access to error and status monitoring registers within the
processor’s PCI configuration space. It also provides insight into thermal monitoring
functions such as TCC activation timers and thermal error logs.
processor’s PCI configuration space. It also provides insight into thermal monitoring
functions such as TCC activation timers and thermal error logs.
The exact list of RAS-related registers in the PCI configuration space can be found in
the Intel® Xeon® Processor 5500 Series Datasheet, Volume 2.
the Intel® Xeon® Processor 5500 Series Datasheet, Volume 2.
Table 6-14. Summary of Processor-specific PECI Commands
Command
Supported on Intel Xeon Processor
5500 Series CPU
Ping()
Yes
GetDIB()
Yes
GetTemp()
Yes
PCIConfigRd()
Yes
PCIConfigWr()
Yes
MbxSend()
1
Yes
MbxGet()
1
Yes