Intel L5506 AT80602002712AA Manuel D’Utilisation
Codes de produits
AT80602002712AA
Intel
®
Xeon
®
Processor 5500 Series Datasheet, Volume 1
15
Intel® Xeon® Processors 5500 Series Electrical Specifications
DDR3 memory frequency are set during manufacturing. It is possible to override the
processor core frequency setting using software. This permits operation at lower core
frequencies than the factory set maximum core frequency.
processor core frequency setting using software. This permits operation at lower core
frequencies than the factory set maximum core frequency.
The processor core frequency is configured during reset by using values stored within
the device during manufacturing. The stored value sets the lowest core multiplier at
which the particular processor can operate. If higher speeds are desired, the
appropriate ratio can be configured via the IA32_PERF_CTL MSR.
the device during manufacturing. The stored value sets the lowest core multiplier at
which the particular processor can operate. If higher speeds are desired, the
appropriate ratio can be configured via the IA32_PERF_CTL MSR.
Clock multiplying within the processor is provided by the internal phase locked loop
(PLL), which requires a constant frequency BCLK_DP, BCLK_DN input, with exceptions
for spread spectrum clocking.
(PLL), which requires a constant frequency BCLK_DP, BCLK_DN input, with exceptions
for spread spectrum clocking.
2.1.6
Test Access Port (TAP) Signals
Due to the voltage levels supported by other components in the Test Access Port (TAP)
logic, it is recommended that the processor(s) be first in the TAP chain and followed by
any other components within the system. A translation buffer should be used to
connect to the rest of the chain unless one of the other components is capable of
accepting an input of the appropriate voltage. Similar considerations must be made for
TCK, TDO, TMS, and TRST#. Two copies of each signal may be required with each
driving a different voltage level.
logic, it is recommended that the processor(s) be first in the TAP chain and followed by
any other components within the system. A translation buffer should be used to
connect to the rest of the chain unless one of the other components is capable of
accepting an input of the appropriate voltage. Similar considerations must be made for
TCK, TDO, TMS, and TRST#. Two copies of each signal may be required with each
driving a different voltage level.
Processor TAP signal DC specifications can be found in
Note:
While TDI, TMS and TRST# do not include On-Die Termination (ODT), these signals are
weakly pulled-up via a 1-5 kΩ resistor to V
TT
.
Note:
While TCK does not include ODT, this signal is weakly pulled-down via a 1-5 kΩ resistor
to V
SS
.
2.1.7
Power / Other Signals
Processors also include various other signals including power/ground, sense points, and
analog inputs. Details can be found in
analog inputs. Details can be found in
and the applicable platform design
guide.
outlines the required voltage supplies necessary to support Intel Xeon
Processor 5500 Series.
Note:
1.
Refer to
for voltage and current specifications.
Further platform and processor power delivery details can be found in the Intel
®
Xeon
®
Processor 5500 Platform Design Guide (PDG).
Table 2-1. Processor Power Supply Voltages
1
Power Rail
Nominal Voltage
Notes
V
CC
;
Each processor includes a dedicated VR11.1 regulator.
V
CCPLL
1.80 V
Each processor includes dedicated V
CCPLL
and PLL circuits.
V
DDQ
1.50 V
Each processor and DDR3 stack shares a dedicated voltage regulator.
V
TTA
, V
TTD
See
;
Each processor includes a dedicated VR11.0 regulator.
V
TT
= V
TTA
+ V
TTD
; P1V1_Vtt is VID[4:2] controlled,
VID range is 1.0255-1.2000V; 20 mV offset (see
); V
TT
represents a typical voltage. V
TT_MIN
and V
TT_MAX
loadlines represent a
31.5 mV offset from V
TT
(typ).