Intel i7-870 BX80605I7870 Manuel D’Utilisation

Codes de produits

BX80605I7870

Datasheet

2.10.19 MC_CHANNEL_0_ODT_MATRIX_RANK_0_3_RD

MC_CHANNEL_1_ODT_MATRIX_RANK_0_3_RD

MC_CHANNEL_2_ODT_MATRIX_RANK_0_3_RD......................................... 74

2.10.20 MC_CHANNEL_0_ODT_MATRIX_RANK_4_7_RD

MC_CHANNEL_1_ODT_MATRIX_RANK_4_7_RD

MC_CHANNEL_2_ODT_MATRIX_RANK_4_7_RD......................................... 75

2.10.21 MC_CHANNEL_0_ODT_MATRIX_RANK_0_3_WR

MC_CHANNEL_1_ODT_MATRIX_RANK_0_3_WR

MC_CHANNEL_2_ODT_MATRIX_RANK_0_3_WR ........................................ 75

2.10.22 MC_CHANNEL_0_ODT_MATRIX_RANK_4_7_WR

MC_CHANNEL_1_ODT_MATRIX_RANK_4_7_WR

MC_CHANNEL_2_ODT_MATRIX_RANK_4_7_WR ........................................ 75

2.10.23 MC_CHANNEL_0_WAQ_PARAMS

MC_CHANNEL_1_WAQ_PARAMS

MC_CHANNEL_2_WAQ_PARAMS ............................................................. 76

2.10.24 MC_CHANNEL_0_SCHEDULER_PARAMS

MC_CHANNEL_1_SCHEDULER_PARAMS

MC_CHANNEL_2_SCHEDULER_PARAMS ................................................... 77

2.10.25 MC_CHANNEL_0_MAINTENANCE_OPS

MC_CHANNEL_1_MAINTENANCE_OPS

MC_CHANNEL_2_MAINTENANCE_OPS ..................................................... 77

2.10.26 MC_CHANNEL_0_TX_BG_SETTINGS

MC_CHANNEL_1_TX_BG_SETTINGS

MC_CHANNEL_2_TX_BG_SETTINGS ........................................................ 78

2.10.27 MC_CHANNEL_0_RX_BGF_SETTINGS

MC_CHANNEL_1_RX_BGF_SETTINGS

MC_CHANNEL_2_RX_BGF_SETTINGS ...................................................... 78

2.10.28 MC_CHANNEL_0_EW_BGF_SETTINGS

MC_CHANNEL_1_EW_BGF_SETTINGS

MC_CHANNEL_2_EW_BGF_SETTINGS...................................................... 79

2.10.29 MC_CHANNEL_0_EW_BGF_OFFSET_SETTINGS

MC_CHANNEL_1_EW_BGF_OFFSET_SETTINGS

MC_CHANNEL_2_EW_BGF_OFFSET_SETTINGS ......................................... 79

2.10.30 MC_CHANNEL_0_ROUND_TRIP_LATENCY

MC_CHANNEL_1_ROUND_TRIP_LATENCY

MC_CHANNEL_2_ROUND_TRIP_LATENCY................................................. 79

2.10.31 MC_CHANNEL_0_PAGETABLE_PARAMS1

MC_CHANNEL_1_PAGETABLE_PARAMS1

MC_CHANNEL_2_PAGETABLE_PARAMS1 .................................................. 80

2.10.32 MC_CHANNEL_0_PAGETABLE_PARAMS2

MC_CHANNEL_1_PAGETABLE_PARAMS2

MC_CHANNEL_2_PAGETABLE_PARAMS2 .................................................. 80

2.10.33 MC_TX_BG_CMD_DATA_RATIO_SETTINGS_CH0

MC_TX_BG_CMD_DATA_RATIO_SETTINGS_CH1

MC_TX_BG_CMD_DATA_RATIO_SETTINGS_CH2 ....................................... 81

2.10.34 MC_TX_BG_CMD_OFFSET_SETTINGS_CH0

MC_TX_BG_CMD_OFFSET_SETTINGS_CH1

MC_TX_BG_CMD_OFFSET_SETTINGS_CH2............................................... 81

2.10.35 MC_TX_BG_DATA_OFFSET_SETTINGS_CH0

MC_TX_BG_DATA_OFFSET_SETTINGS_CH1

MC_TX_BG_DATA_OFFSET_SETTINGS_CH2 ............................................. 81

2.10.36 MC_CHANNEL_0_ADDR_MATCH

MC_CHANNEL_1_ADDR_MATCH

MC_CHANNEL_2_ADDR_MATCH.............................................................. 82

2.10.37 MC_CHANNEL_0_ECC_ERROR_MASK

MC_CHANNEL_1_ECC_ERROR_MASK

MC_CHANNEL_2_ECC_ERROR_MASK....................................................... 83

2.10.38 MC_CHANNEL_0_ECC_ERROR_INJECT

MC_CHANNEL_1_ECC_ERROR_INJECT

MC_CHANNEL_2_ECC_ERROR_INJECT..................................................... 83