Motorola DSP56012 Manuel D’Utilisation
4-16
DSP56012 User’s Manual
MOTOROLA
Parallel Host Interface
Host Interface (HI)
Note:
Hardware reset and software reset clear HF3.
Note:
There are four general purpose host flags: two used by the host to signal the
DSP (HF0 and HF1), and two used by the DSP to signal the host processor
(HF2 and HF3). They are not designated for any specific purpose. These four
flags do not generate interrupts; they must be polled. These flags can be used
individually or as encoded pairs. See
DSP (HF0 and HF1), and two used by the DSP to signal the host processor
(HF2 and HF3). They are not designated for any specific purpose. These four
flags do not generate interrupts; they must be polled. These flags can be used
individually or as encoded pairs. See
Section
example of the usage of host flags is the bootstrap loader, which is listed in
Appendix A
.
HI flags are used to signal the bootstrap program whether or not
to terminate early.
4.4.4.1.6
HCR Reserved—Bits 5, 6, and 7
These unused bits are reserved for expansion and should be written with 0s for
compatibility with future revisions.
compatibility with future revisions.
4.4.4.2
HI Status Register (HSR)
The HI Status Register (HSR) is an 8-bit read-only status register used by the DSP to
interrogate the HI status and flags bits. The HSR can not be directly accessed by the
host processor. When the HSR is read to the internal data bus, the register contents
occupy the low-order byte of the data bus; the high-order portion is 0-filled. The HSR
status bits are described in the following paragraphs.
interrogate the HI status and flags bits. The HSR can not be directly accessed by the
host processor. When the HSR is read to the internal data bus, the register contents
occupy the low-order byte of the data bus; the high-order portion is 0-filled. The HSR
status bits are described in the following paragraphs.
4.4.4.2.1
HSR HI Receive Data Full (HRDF)—Bit 0
The HI Receive Data Full (HRDF) bit indicates that the HI Receive data register
(HORX) contains data from the host processor. HRDF is set when data is transferred
from the TXH:TXM:TXL registers to the HORX register. HRDF is cleared when
HORX is read by the DSP. HRDF can also be cleared by the host processor using the
initialize function.
(HORX) contains data from the host processor. HRDF is set when data is transferred
from the TXH:TXM:TXL registers to the HORX register. HRDF is cleared when
HORX is read by the DSP. HRDF can also be cleared by the host processor using the
initialize function.
Note:
Hardware reset, software reset, individual reset, and Stop mode clear HRDF.
4.4.4.2.2
HSR HI Transmit Data Empty (HTDE)—Bit 1
The HI Transmit Data Empty (HTDE) bit indicates that the HI Transmit data register
(HOTX) is empty and can be written by the DSP. HTDE is set when the HOTX
register is transferred to the RXH:RXM:RXL registers. HTDE is cleared when HOTX
is written by the DSP. HTDE can also be set by the host processor using the initialize
function.
(HOTX) is empty and can be written by the DSP. HTDE is set when the HOTX
register is transferred to the RXH:RXM:RXL registers. HTDE is cleared when HOTX
is written by the DSP. HTDE can also be set by the host processor using the initialize
function.
Note:
Hardware reset, software reset, individual reset, and Stop mode set HTDE.