Renesas R5S72641 Manuel D’Utilisation
Section 2 CPU
R01UH0134EJ0400 Rev. 4.00
Page 71 of 2108
Sep 24, 2014
SH7262 Group, SH7264 Group
Classification
Types
Operation
Code
Code
Function
No. of
Instructions
Instructions
Logic
operations
operations
6 AND Logical
AND
14
NOT Bit
inversion
OR Logical
OR
TAS
Memory test and bit set
TST
Logical AND and T bit set
XOR
Exclusive
OR
Shift
12
ROTL
One-bit left rotation
16
ROTR
One-bit right rotation
ROTCL
One-bit left rotation with T bit
ROTCR
One-bit right rotation with T bit
SHAD
Dynamic arithmetic shift
SHAL
One-bit arithmetic left shift
SHAR
One-bit arithmetic right shift
SHLD
Dynamic logical shift
SHLL
One-bit logical left shift
SHLLn
n-bit logical left shift
SHLR
One-bit logical right shift
SHLRn
n-bit logical right shift
Branch
10
BF
Conditional branch, conditional delayed branch
(branch when T = 0)
(branch when T = 0)
15
BT
Conditional branch, conditional delayed branch
(branch when T = 1)
(branch when T = 1)
BRA
Unconditional delayed branch
BRAF
Unconditional delayed branch
BSR
Delayed branch to subroutine procedure
BSRF
Delayed branch to subroutine procedure
JMP
Unconditional delayed branch
JSR
Branch to subroutine procedure
Delayed branch to subroutine procedure
RTS
Return from subroutine procedure
Delayed return from subroutine procedure
RTV/N
Return from subroutine procedure with Rm
R0 transfer