Xilinx PCI32 Manuel D’Utilisation

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DS206 August 31, 2005

Other FPGA resources that can be used in conjunction with the core to enable efficient implementation
of a PCI system include:

• Block SelectRAM™ memory. Blocks of on-chip ultra-fast RAM with synchronous write and 

dual-port RAM capabilities. Used in PCI designs to implement FIFOs.

• SelectRAM memory. Distributed on-chip ultra-fast RAM with synchronous write option and 

dual-port RAM capabilities. Used in PCI designs to implement FIFOs.

• Internal three-state bus capability for data multiplexing.

The interface is carefully optimized for best possible performance and utilization in Xilinx FPGA
devices.

Drawing on the architectural advantages of Xilinx FPGAs, Xilinx Smart-IP technology ensures the
highest performance, predictability, repeatability, and flexibility in PCI designs. The Smart-IP technol-
ogy is incorporated in every PCI interface.

Xilinx Smart-IP technology leverages the Xilinx architectural advantages, such as look-up tables and
segmented routing, as well as floorplanning information, such as logic mapping and location con-
straints. This technology provides the best physical layout, predictability, and performance. In addi-
tion, these features allow for significantly reduced compile times over competing architectures.

To guarantee the critical setup, hold, minimum clock-to-out, and maximum clock-to-out timing, the
PCI interface is delivered with Smart-IP constraint files that are unique for a device and package com-
bination. These constraint files guide the implementation tools so that the critical paths always are
within specification.

Xilinx provides Smart-IP constraint files for many device and package combinations. Constraint files
for unsupported device and package combinations may be generated using the web-based constraint
file generator.