Freescale Semiconductor MCF52212 Manuel D’Utilisation
Power Management
MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor
8-9
8.3
IPS Bus Timeout Monitor
The IPS controller implements a bus timeout monitor to ensure that every IPS bus cycle is properly
terminated within a programmed period of time. The monitor continually checks for termination of each
IPS bus cycle and completes the cycle if there is no response when the programmed monitor cycle count
is reached. The error termination is propagated onto the system bus and eventually back to the ColdFire
Core.
terminated within a programmed period of time. The monitor continually checks for termination of each
IPS bus cycle and completes the cycle if there is no response when the programmed monitor cycle count
is reached. The error termination is propagated onto the system bus and eventually back to the ColdFire
Core.
The monitor can be programmed from 8–1024 system bus cycles under control of the IPS Bus Monitor
Timeout Register (IPSBMT). The timeout value must be selected so that it is larger than the response time
of the slowest IPS peripheral device. The bus timeout monitor begins counting on the initial assertion of
any IPS module enable and continues to count until the bus cycle is terminated via the negation of
ips_xfr_wait. If the programmed timeout value is reached before a termination, the bus monitor completes
Timeout Register (IPSBMT). The timeout value must be selected so that it is larger than the response time
of the slowest IPS peripheral device. The bus timeout monitor begins counting on the initial assertion of
any IPS module enable and continues to count until the bus cycle is terminated via the negation of
ips_xfr_wait. If the programmed timeout value is reached before a termination, the bus monitor completes
Table 8-8. LPCR Field Descriptions
Field
Description
7–6
LPMD
Low-power mode select. Used to select the low-power mode the chip enters after the ColdFire CPU executes the
STOP instruction. These bits must be written prior to instruction execution for them to take effect. The LPMD[1:0]
bits are readable and writable in all modes. Below illustrates the four different power modes that can be configured
with the LPMD bit field.
STOP instruction. These bits must be written prior to instruction execution for them to take effect. The LPMD[1:0]
bits are readable and writable in all modes. Below illustrates the four different power modes that can be configured
with the LPMD bit field.
Note: If LPCR[LPMD] is cleared, the device stops executing code upon issue of a STOP instruction. However, no
clocks are disabled.
5
Reserved, should be cleared.
4–3
STPMD
CLKOUT stop mode. This field controls CLKOUT operation during stop mode.
2
Reserved, should be cleared.
1
LVDSE
LVD Standby Enable bit. This bit controls whether the PMM enters VREG Standby Mode (LVD disabled) or VREG
Pseudo-Standby (LVD enabled) mode when the PMM receives a power down request. This bit has no
effect if RCR[LVDE] is cleared (see
Pseudo-Standby (LVD enabled) mode when the PMM receives a power down request. This bit has no
effect if RCR[LVDE] is cleared (see
0 VREG Standby mode (LVD disabled on power down request).
1 VREG Pseudo-Standby mode (LVD enabled on power down request).
1 VREG Pseudo-Standby mode (LVD enabled on power down request).
0
Reserved, should be cleared.
LPMD[1:0]
Mode
11
STOP
10
WAIT
01
DOZE
00
RUN
Operation During Stop Mode
STPMD[1:0]
System Clocks
CLKOUT
PLL
OSC
PMM
00
Disabled
Enabled
Enabled
Enabled
Enabled
01
Disabled
Disabled
Enabled
Enabled
Enabled
10
Disabled
Disabled
Disabled
Enabled
Enabled
11
Disabled
Disabled
Disabled
Disabled
Low Power Option