Freescale Semiconductor MCF52212 Manuel D’Utilisation
System Control Module (SCM)
MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2
12-12
Freescale Semiconductor
The initial state of the master priorities is M2 > M0. System software should guarantee that the
programmed Mn_PRTY fields are unique, otherwise the hardware defaults to the initial-state priorities.
programmed Mn_PRTY fields are unique, otherwise the hardware defaults to the initial-state priorities.
12.7
System Access Control Unit (SACU)
This section details the functionality of the system access control unit (SACU), which provides the
mechanism needed to implement secure bus transactions to the address space mapped to the internal
modules.
mechanism needed to implement secure bus transactions to the address space mapped to the internal
modules.
12.7.1
Overview
The SACU supports the traditional model of two privilege levels: supervisor and user. Typically, memory
references with the supervisor attribute have total accessibility to all the resources in the system, while user
mode references cannot access system control and configuration registers. In many systems, the operating
system executes in supervisor mode, while application software executes in user mode.
references with the supervisor attribute have total accessibility to all the resources in the system, while user
mode references cannot access system control and configuration registers. In many systems, the operating
system executes in supervisor mode, while application software executes in user mode.
The SACU further partitions the access control functions into two parts: one control register defines the
privilege level associated with each bus master, and another set of control registers define the access levels
associated with the peripheral modules and memory space.
privilege level associated with each bus master, and another set of control registers define the access levels
associated with the peripheral modules and memory space.
The SACU’s programming model is physically implemented as part of the system control module (SCM)
with the actual access control logic included as part of the arbitration controller. Each bus transaction
targeted for the IPS space is first checked to see if its privilege rights allow access to the given memory
space. If the privilege rights are correct, the access proceeds on the bus. If the privilege rights are
insufficient for the targeted memory space, the transfer is immediately aborted and terminated with an
exception, and the targeted module is not accessed.
with the actual access control logic included as part of the arbitration controller. Each bus transaction
targeted for the IPS space is first checked to see if its privilege rights allow access to the given memory
space. If the privilege rights are correct, the access proceeds on the bus. If the privilege rights are
insufficient for the targeted memory space, the transfer is immediately aborted and terminated with an
exception, and the targeted module is not accessed.
12.7.2
Features
Each bus transfer can be classified by its privilege level and the reference type. The complete set of access
types includes the following:
types includes the following:
•
Supervisor instruction fetch
•
Supervisor operand read
•
Supervisor operand write
•
User instruction fetch
•
User operand read
12
PRKLAST
Park on the last active master or highest priority master if no masters are active
0 park on last active master
1 park on highest priority master
0 park on last active master
1 park on highest priority master
11–8
LCKOUT_TIME
Lock-out Time. Lock-out time for a master being denied the bus.
The lock out time is defined as 2^ LCKOUT_TIME[3:0].
The lock out time is defined as 2^ LCKOUT_TIME[3:0].
7–0
Reserved, should be cleared.
Table 12-7. MPARK Field Description (continued)
Field
Description