Freescale Semiconductor MCF52212 Manuel D’Utilisation
Multiply-Accumulate Unit (MAC)
MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor
4-3
BDM: 0x804 (MACSR)
Access: Supervisor read/write
BDM read/write
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
OMC S/U
F/I
R/T
N
Z
V
C
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0
0
0
0
0
0
0
0
Figure 4-2. MAC Status Register (MACSR)
Table 4-2. MACSR Field Descriptions
Field
Description
31–8
Reserved, must be cleared.
7
OMC
Overflow saturation mode. Enables or disables saturation mode on overflow. If set, the accumulator is set
to the appropriate constant on any operation that overflows the accumulator. After saturation, the
accumulator remains unaffected by any other MAC or MSAC instructions until the overflow bit is cleared or
the accumulator is directly loaded.
to the appropriate constant on any operation that overflows the accumulator. After saturation, the
accumulator remains unaffected by any other MAC or MSAC instructions until the overflow bit is cleared or
the accumulator is directly loaded.
6
S/U
Signed/unsigned operations.
In integer mode:
S/U determines whether operations performed are signed or unsigned. It also determines the accumulator
value during saturation, if enabled.
0 Signed numbers. On overflow, if OMC is enabled, the accumulator saturates to the most positive
In integer mode:
S/U determines whether operations performed are signed or unsigned. It also determines the accumulator
value during saturation, if enabled.
0 Signed numbers. On overflow, if OMC is enabled, the accumulator saturates to the most positive
(0x7FFF_FFFF) or the most negative (0x8000_0000) number, depending on the instruction and the
product value that overflowed.
product value that overflowed.
1 Unsigned numbers. On overflow, if OMC is enabled, the accumulator saturates to the smallest value
(0x0000_0000) or the largest value (0xFFFF_FFFF), depending on the instruction.
In fractional mode:
S/U controls rounding while storing the accumulator to a general-purpose register.
0 Move accumulator without rounding to a 16-bit value. Accumulator is moved to a general-purpose
S/U controls rounding while storing the accumulator to a general-purpose register.
0 Move accumulator without rounding to a 16-bit value. Accumulator is moved to a general-purpose
register as a 32-bit value.
1 The accumulator is rounded to a 16-bit value using the round-to-nearest (even) method when moved to
a general-purpose register. See
. The resulting 16-bit value is stored in the
lower word of the destination register. The upper word is zero-filled. This rounding procedure does not
affect the accumulator value.
affect the accumulator value.
5
F/I
Fractional/integer mode. Determines whether input operands are treated as fractions or integers.
0 Integers can be represented in signed or unsigned notation, depending on the value of S/U.
1 Fractions are represented in signed, fixed-point, two’s complement notation. Values range from -1 to
0 Integers can be represented in signed or unsigned notation, depending on the value of S/U.
1 Fractions are represented in signed, fixed-point, two’s complement notation. Values range from -1 to
1 - 2
-15
for 16-bit fractions and -1 to 1 - 2
-31
for 32-bit fractions. See
4
R/T
Round/truncate mode. Controls rounding procedure for MSAC.L instructions when in fractional mode.
0 Truncate. The product’s lsbs are dropped before it is combined with the accumulator.
1 Round-to-nearest (even). The 64-bit product of two 32-bit, fractional operands is rounded to the nearest
0 Truncate. The product’s lsbs are dropped before it is combined with the accumulator.
1 Round-to-nearest (even). The 64-bit product of two 32-bit, fractional operands is rounded to the nearest
32-bit value. If the low-order 32 bits equal 0x8000_0000, the upper 32 bits are rounded to the nearest
even (lsb = 0) value. See
even (lsb = 0) value. See
.
3
N
Negative. Set if the msb of the result is set, otherwise cleared. N is affected only by MAC, MSAC, and load
operations; it is not affected by MULS and MULU instructions.
operations; it is not affected by MULS and MULU instructions.
2
Z
Z
Zero. Set if the result equals zero, otherwise cleared. This bit is affected only by MAC, MSAC, and load
operations; it is not affected by MULS and MULU instructions.
operations; it is not affected by MULS and MULU instructions.