Compaq EV67 Manuel D’Utilisation

Integer issue queue

,

pipelined

,

Internal processor registers

,

accessing

,

explicitly written

,

implicitly written

,

ordering access

,

paired fetch order

,

scoreboard bits for

,

INTERRUPT interrupt

,

INVAL_TO_DIRTY Cbox CSR

,

programming

,

INVAL_TO_DIRTY_ENABLE Cbox CSR

,

, 

InvalToDirty, 21264/EV67 command

,

, 

system probes, with

,

InvalToDirtyVic, 21264/EV67 command

,

, 

IRQ_H signal pins

,

Istream

,

Istream memory references

translation to external references

,

ISTREAM_BC_DBL error status in C_STAT

,

ISTREAM_BC_ERR error status in C_STAT

,

ISTREAM_MEM_DBL error status in C_STAT

,

ISTREAM_MEM_ERR error status in C_STAT

,

ISUM interrupt summary register

,

at power-on reset state

,

ITB

,

ITB fill

,

ITB miss, pipeline abort delay with

,

ITB_IA invalidate-all register

,

at power-on reset state

,

ITB_IAP invalidate-all (ASM=0) register

,

at power-on reset state

,

ITB_IS invalidate single register

,

at power-on reset state

,

ITB_MISS fault

,

ITB_PTE array write register

,

at power-on reset state

,

ITB_TAG array write register

,

at power-on reset state

,

IVA_FORM instruction virtual address format 

register

,

at power-on reset state

,

JITTER_CMD Cbox CSR, defined

,

JMP misprediction, in PALcode

,

JSR misprediction

in PALcode

,

pipeline abort delay with

,

JSR_COR misprediction, in PALcode

,

Junction temperature

,

Late-write non-bursting SSRAM pin assignments

,

LDBU instruction, normal prefetch with

,

LDF instruction, normal prefetch with

,

LDG instruction, normal prefetch with

,

LDQ instruction, prefetch with evict next

,

LDS instruction, prefetch with modify intent

,

LDT instruction, normal prefetch with

,

LDWU instruction, normal prefetch with

,

LDx_L instructions

in-order processing for

,

locking mechanism for

,

Load hit speculation

,

Load instructions

ECC with

,

I/O reference ordering

,

Mbox order traps

,

memory reference ordering

,

translation to external interface

,

Load queue, described

,

Load-load order trap

,

Local predictor

,

Lock mechanism

,

Logic symbol, the 21264/EV67

,

M_CTL Mbox control register

,

at power-on reset state

,

MB instruction processing

,