Fujitsu MB91191 Manuel D’Utilisation

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5.4

Port 2, 3

Ports 2 and 3 function as input/output ports under single-chip mode, and function as
the address/data bus under external bus mode.

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Functions of I/O Port 2, 3

Each port has two registers per bit, namely DDR and PDR, and input/output can be set independently per

bit. Pins whose DDR is "1" are set to Output, whereas pins whose DDR is "0" are set to Input.

The PDR is undefined by a reset the DDR is cleared to "0" and set to Input.

In terms of the DDR specification per bit, for output setup, the value written to the PDR is output to the pin,

and the PDR contents are read as the read value of the PDR in this case.

At the time of the input setup, the pin will have high impedance status. At this time, the pin level is read

from the read value of the PDR.

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Block Diagram of Port 2, 3

Figure 5.4-1 Block Diagram of Port 2, 3

P27 to P20
P37 to P30

Bus signal

Bus control

PDR

DDR

Data register read