Fujitsu MB91191 Manuel D’Utilisation
65
3.12.4
Gear Control Register (GCR)
The gear control register controls the gear functions of the CPU and peripheral clocks.
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Gear Control Register (GCR)
Figure 3.12-6 Gear Control Register (GCR)
[bit7, 6]:CCK1, 0
These bits specify the CPU gear cycle. The bits and selected cycles have the following relationship.
These bits are initialized by a reset.
CCK1
CCK0
PCK1
PCK0
CHC 11--11-1
B
Initial value
R/W
R/W
R/W
R/W
R/W
7
6
5
4
3
2
1
0
Address: 000484
H
Access
bit
Table 3.12-3 CPU machine clock
CCK1 CCK0 CHC
CPU machine clock
(source oscillation: input frequency from X0)
0 0 0
Source
oscillation
× 1
0 1 0
Source
oscillation
× 1/2
1 0 0
Source
oscillation
× 1/4
1 1 0
Source
oscillation
× 1/8
0 0 1
Source
oscillation
× 1/2
0 1 1
Source
oscillation
× 1/2 × 1/2
1 0 1
Source
oscillation
× 1/2 × 1/4
1 1 1
Source
oscillation
× 1/2 × 1/8 (Initial value)