Fujitsu FR20 Manuel D’Utilisation
242
CHAPTER 16 10-bit A/D Converter
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Soft Conversion FIFO Data Register (SCFD)
Figure 16.2-5 Soft conversion FIFO data register (SCFD)
It is conversion result register for soft start. Reading this register enables data to be fetched sequentially.
[bit11, 10]:
It is an unused bit.
[bit15 to 12]:C3 to 0
It is input channel of conversion result.
[bit9 to 0]:D9 to 0
It is soft conversion data.
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Hard Conversion Status Register (HCSR)
Figure 16.2-6 Hard Conversion Status Register (HCSR)
[bit7]:HCEF
It is hard conversion end flag.
[bit6]:HECR
It is HCEF clear bit.
The read value of this bit is always "1".
XXXX --XX
H
XXXX XXXX
H
Initial value
bit
R
C3
C2
C1
C0
D9 D8
D7
D6
D5
D4
D3
D2
D1
D0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Address: 0000A6
H
Access
C3 C2 C1 C0
Channel
supported
by
conversion result
0 0 0 0
AN-0
0 0 0 1
AN-1
0 to 1
0 to 1
1 to 1
0 to 0
AN-2 to AN-E
1 1 1 1
AN-F
7 6 5 4 3 2 1 0
X10- -001
B
Initial value
bit
HCEF
HECR
HCIE
HFCR
HFUL
HEMP
R
R/W
R
R
W
W
Address: 0000A9
H
Access
0
None or Under the conversion
1 Conversion
complete
0
Clear hard conversion end flag.
1 None