Silicon Laboratories C8051F343 Manuel D’Utilisation
Rev. 0.5
235
C8051F340/1/2/3/4/5/6/7
Figure 20.6. Slave Mode Data/Clock Timing (CKPHA = 0)
Figure 20.7. Slave Mode Data/Clock Timing (CKPHA = 1)
MSB
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
MISO
NSS (4-Wire Mode)
MSB
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
MOSI
SCK
(CKPOL=0, CKPHA=0)
(CKPOL=0, CKPHA=0)
SCK
(CKPOL=1, CKPHA=0)
(CKPOL=1, CKPHA=0)
SCK
(CKPOL=0, CKPHA=1)
(CKPOL=0, CKPHA=1)
SCK
(CKPOL=1, CKPHA=1)
(CKPOL=1, CKPHA=1)
MSB
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
MISO
NSS (4-Wire Mode)
MSB
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
MOSI