Silicon Laboratories C8051F343 Manuel D’Utilisation
C8051F340/1/2/3/4/5/6/7
24
Rev. 0.5
1.3.
Universal Serial Bus Controller
The Universal Serial Bus Controller (USB0) is a USB 2.0 compliant Full or Low Speed function with inte-
grated transceiver and endpoint FIFO RAM. A total of eight endpoint pipes are available: a bi-directional
control endpoint (Endpoint0) and three pairs of IN/OUT endpoints (Endpoints1-3 IN/OUT).
grated transceiver and endpoint FIFO RAM. A total of eight endpoint pipes are available: a bi-directional
control endpoint (Endpoint0) and three pairs of IN/OUT endpoints (Endpoints1-3 IN/OUT).
A 1k Byte block of RAM is used for USB FIFO space. This FIFO space is distributed among Endpoints0-3;
Endpoint1-3 FIFO slots can be configured as IN, OUT, or both IN and OUT (split mode). The maximum
FIFO size is 512 bytes (Endpoint3).
Endpoint1-3 FIFO slots can be configured as IN, OUT, or both IN and OUT (split mode). The maximum
FIFO size is 512 bytes (Endpoint3).
USB0 can be operated as a Full or Low Speed function. On-chip 4x Clock Multiplier and clock recovery cir-
cuitry allow both Full and Low Speed options to be implemented with the on-chip precision oscillator as the
USB clock source. An external oscillator source can also be used with the 4x Clock Multiplier to generate
the USB clock. The CPU clock source is independent of the USB clock.
cuitry allow both Full and Low Speed options to be implemented with the on-chip precision oscillator as the
USB clock source. An external oscillator source can also be used with the 4x Clock Multiplier to generate
the USB clock. The CPU clock source is independent of the USB clock.
The USB Transceiver is USB 2.0 compliant, and includes on-chip matching and pull-up resistors. The
pull-up resistors can be enabled/disabled in software, and will appear on the D+ or D- pin according to the
software-selected speed setting (Full or Low Speed).
pull-up resistors can be enabled/disabled in software, and will appear on the D+ or D- pin according to the
software-selected speed setting (Full or Low Speed).
Figure 1.5. USB Controller Block Diagram
Transceiver
Serial Interface Engine (SIE)
USB FIFOs
(1k RAM)
D+
D-
VDD
Endpoint0
IN/OUT
Endpoint1
IN
OUT
Endpoint2
IN
OUT
Endpoint3
IN
OUT
Data
Transfer
Control
CIP-51 Core
USB
Control,
Status, and
Interrupt
Registers