Silicon Laboratories C8051F344 Manuel D’Utilisation
C8051F340/1/2/3/4/5/6/7
150
Rev. 0.5
Figure 15.4. Crossbar Priority Decoder with Crystal Pins Skipped
Registers XBR0, XBR1, and XBR2 are used to assign the digital I/O resources to the physical I/O Port
pins. Note that when the SMBus is selected, the Crossbar assigns both pins associated with the SMBus
(SDA and SCL); when either UART is selected, the Crossbar assigns both pins associated with the UART
(TX and RX). UART0 pin assignments are fixed for bootloading purposes: UART TX0 is always assigned
to P0.4; UART RX0 is always assigned to P0.5. Standard Port I/Os appear contiguously after the prioritized
functions have been assigned.
pins. Note that when the SMBus is selected, the Crossbar assigns both pins associated with the SMBus
(SDA and SCL); when either UART is selected, the Crossbar assigns both pins associated with the UART
(TX and RX). UART0 pin assignments are fixed for bootloading purposes: UART TX0 is always assigned
to P0.4; UART RX0 is always assigned to P0.5. Standard Port I/Os appear contiguously after the prioritized
functions have been assigned.
Important Note: The SPI can be operated in either 3-wire or 4-wire modes, depending on the state of the
NSSMD1-NSSMD0 bits in register SPI0CN. According to the SPI mode, the NSS signal may or may not be
routed to a Port pin.
NSSMD1-NSSMD0 bits in register SPI0CN. According to the SPI mode, the NSS signal may or may not be
routed to a Port pin.
XT
A
L
1
XT
A
L
2
C
N
VST
R
VR
EF
XT
A
L
1
XT
A
L
2
AL
E
C
N
VST
R
VR
EF
/R
D
/W
R
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
SCK
MISO
MOSI
NSS*
*NSS is only pinned out in 4-wire SPI mode
CP0
CP0A
CP1
T1
TX1**
**UART1 Only in 48-pin Package
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
SDA
SCL
CP1A
CEX3
CEX4
CEX2
CEX0
CEX1
SYSCLK
P0
P1
Special Function Signals are not assigned by the Crossbar. When these signals are
enabled, the Crossbar must be manually configured to skip their corresponding port pins.
enabled, the Crossbar must be manually configured to skip their corresponding port pins.
Port pin potentially available to peripheral
P0SKIP[0:7]
P1SKIP[0:7]
P2
SF Signals
ECI
T0
RX1**
P3
P3.1-P3.7 Unavailable on
32-pin Package
SF Signals
(48-pin
Package)
(48-pin
Package)
P2SKIP[0:7]
P3SKIP[0:7]
SF Signals
(32-pin
Package)
(32-pin
Package)
PIN I/O
TX0
RX0