Silicon Laboratories C8051F344 Manuel D’Utilisation
Rev. 0.5
229
C8051F340/1/2/3/4/5/6/7
20. Enhanced Serial Peripheral Interface (SPI0)
The Enhanced Serial Peripheral Interface (SPI0) provides access to a flexible, full-duplex synchronous
serial bus. SPI0 can operate as a master or slave device in both 3-wire or 4-wire modes, and supports mul-
tiple masters and slaves on a single SPI bus. The slave-select (NSS) signal can be configured as an input
to select SPI0 in slave mode, or to disable Master Mode operation in a multi-master environment, avoiding
contention on the SPI bus when more than one master attempts simultaneous data transfers. NSS can
also be configured as a chip-select output in master mode, or disabled for 3-wire operation. Additional gen-
eral purpose port I/O pins can be used to select multiple slave devices in master mode.
serial bus. SPI0 can operate as a master or slave device in both 3-wire or 4-wire modes, and supports mul-
tiple masters and slaves on a single SPI bus. The slave-select (NSS) signal can be configured as an input
to select SPI0 in slave mode, or to disable Master Mode operation in a multi-master environment, avoiding
contention on the SPI bus when more than one master attempts simultaneous data transfers. NSS can
also be configured as a chip-select output in master mode, or disabled for 3-wire operation. Additional gen-
eral purpose port I/O pins can be used to select multiple slave devices in master mode.
Figure 20.1. SPI Block Diagram
SFR Bus
Data Path
Control
SFR Bus
Write
SPI0DAT
Receive Data Buffer
SPI0DAT
0
1
2
3
4
5
6
7
Shift Register
SPI CONTROL LOGIC
SPI0CKR
SC
R
7
SC
R
6
SC
R
5
SC
R
4
SC
R
3
SC
R
2
SC
R
1
SC
R
0
SPI0CFG
SPI0CN
Pin Interface
Control
Pin
Control
Logic
C
R
R
O
S
S
B
A
R
S
B
A
R
Port I/O
Read
SPI0DAT
SPI IRQ
Tx Data
Rx Data
SCK
MOSI
MISO
NSS
Transmit Data Buffer
Clock Divide
Logic
SYSCLK
CKPHA
CKP
O
L
S
L
VSE
L
NS
SM
D1
NS
SM
D0
SP
IB
SY
MS
T
E
N
NSS
IN
SR
M
T
RX
BM
T
SP
IF
WC
OL
MO
D
F
RX
OVRN
TX
BMT
SP
IE
N