Manuel D’Utilisation (KC.34501.XLX)Table des matières1 Introduction91.1 Processor Feature Details111.1.1 Supported Technologies111.2 Interfaces111.2.1 System Memory Support111.2.2 PCI Express*121.2.3 Direct Media Interface (DMI)131.2.4 Platform Environment Control Interface (PECI)141.3 Power Management Support141.3.1 Processor Core141.3.2 System141.3.3 Memory Controller141.3.4 PCI Express*141.4 Thermal Management Support151.5 Package151.6 Terminology151.7 Related Documents172 Interfaces192.1 System Memory Interface192.1.1 System Memory Technology Supported192.1.2 System Memory Timing Support212.1.3 System Memory Organization Modes212.1.3.1 Single-Channel Mode212.1.3.2 Dual-Channel Mode—Intel® Flex Memory Technology Mode222.1.4 Rules for Populating Memory Slots232.1.5 Technology Enhancements of Intel® Fast Memory Access (Intel® FMA)242.1.5.1 Just-in-Time Command Scheduling242.1.5.2 Command Overlap242.1.5.3 Out-of-Order Scheduling242.1.6 System Memory Pre-Charge Power Down Support Details242.2 PCI Express* Interface252.2.1 PCI Express* Architecture252.2.1.1 Transaction Layer262.2.1.2 Data Link Layer262.2.1.3 Physical Layer262.2.2 PCI Express* Configuration Mechanism272.2.3 PCI Express* Ports and Bifurcation282.2.3.1 PCI Express* Bifurcated Mode282.3 Direct Media Interface (DMI)282.3.1 DMI Error Flow282.3.2 Processor/PCH Compatibility Assumptions282.3.3 DMI Link Down282.4 Platform Environment Control Interface (PECI)292.5 Interface Clocking292.5.1 Internal Clocking Requirements293 Technologies313.1 Intel® Virtualization Technology313.1.1 Intel® VT-x Objectives313.1.2 Intel® VT-x Features313.1.3 Intel® VT-d Objectives323.1.4 Intel® VT-d Features323.1.5 Intel® VT-d Features Not Supported333.2 Intel® Trusted Execution Technology (Intel® TXT)333.3 Intel® Hyper-Threading Technology343.4 Intel® Turbo Boost Technology344 Power Management354.1 ACPI States Supported354.1.1 System States354.1.2 Processor Core/Package Idle States354.1.3 Integrated Memory Controller States354.1.4 PCI Express* Link States364.1.5 Interface State Combinations364.2 Processor Core Power Management364.2.1 Enhanced Intel® SpeedStep® Technology374.2.2 Low-Power Idle States374.2.3 Requesting Low-Power Idle States394.2.4 Core C-states394.2.4.1 Core C0 State404.2.4.2 Core C1/C1E State404.2.4.3 Core C3 State404.2.4.4 Core C6 State404.2.4.5 C-State Auto-Demotion404.2.5 Package C-States414.2.5.1 Package C0424.2.5.2 Package C1/C1E424.2.5.3 Package C3 State434.2.5.4 Package C6 State434.3 IMC Power Management434.3.1 Disabling Unused System Memory Outputs434.3.2 DRAM Power Management and Initialization444.3.2.1 Initialization Role of CKE444.3.2.2 Conditional Self-Refresh444.3.2.3 Dynamic Power Down Operation444.3.2.4 DRAM I/O Power Management454.4 PCI Express* Power Management455 Thermal Management476 Signal Description496.1 System Memory Interface506.2 Memory Reference and Compensation526.3 Reset and Miscellaneous Signals526.4 PCI Express* Based Interface Signals536.5 DMI—Processor to PCH Serial Interface536.6 PLL Signals546.7 Intel® Flexible Display Interface Signals546.8 JTAG/ITP Signals556.9 Error and Thermal Protection566.10 Power Sequencing576.11 Processor Core Power Signals576.12 Graphics and Memory Core Power Signals596.13 Ground and NCTF606.14 Processor Internal Pull Up/Pull Down607 Electrical Specifications617.1 Power and Ground Lands617.2 Decoupling Guidelines617.2.1 Voltage Rail Decoupling617.3 Processor Clocking (BCLK[0], BCLK#[0])627.3.1 PLL Power Supply627.4 VCC Voltage Identification (VID)627.5 Reserved or Unused Signals667.6 Signal Groups667.7 Test Access Port (TAP) Connection697.8 Absolute Maximum and Minimum Ratings697.9 DC Specifications707.9.1 Voltage and Current Specifications707.10 Platform Environmental Control Interface (PECI) DC Specifications777.10.1 DC Characteristics777.10.2 Input Device Hysteresis788 Processor Land and Signal Information798.1 Processor Land Assignments79Taille: 500 koPages: 98Language: EnglishOuvrir le manuel
