Manuels d'utilisation pour AMD LX 800@0.9W

Table des matières

• List of Figures

  5
• List of Tables

  7
• Overview

  11
  • 1.1 General Description

    11
  • 1.2 Features

    12
• Architecture Overview

  15
  • 2.1 CPU Core

    15
    • 2.1.1 Integer Unit

      15
    • 2.1.2 Memory Management Unit

      16
    • 2.1.3 Cache and TLB Subsystem

      16
    • 2.1.4 Bus Controller Unit

      16
    • 2.1.5 Floating Point Unit

      16
  • 2.2 GeodeLink™ Control Processor

    16
  • 2.3 GeodeLink™ Interface Units

    16
  • 2.4 GeodeLink™ Memory Controller

    16
  • 2.5 Graphics Processor

    17
  • 2.6 Display Controller

    18
  • 2.7 Video Processor

    18
    • 2.7.1 CRT Interface

      18
    • 2.7.2 TFT Controller

      18
    • 2.7.3 Video Output Port

      18
  • 2.8 Video Input Port

    18
  • 2.9 GeodeLink™ PCI Bridge

    18
  • 2.10 Security Block

    19
• Signal Definitions

  21
  • 3.1 Buffer Types

    23
  • 3.2 Bootstrap Options

    24
  • 3.3 Ball Assignments

    24
  • 3.4 Signal Descriptions

    33
    • 3.4.1 System Interface Signals

      33
    • 3.4.2 PLL Interface Signals

      34
    • 3.4.3 Memory Interface Signals (DDR)

      35
    • 3.4.4 Internal Test and Measurement Interface Signals

      36
    • 3.4.5 PCI Interface Signals

      37
    • 3.4.6 TFT Display Interface Signals

      40
    • 3.4.7 CRT Display Interface Signals

      41
    • 3.4.8 VIP Interface Signals

      41
    • 3.4.9 Power and Ground Interface Signals

      42
• GeodeLink™ Interface Unit

  45
  • 4.1 MSR Set

    45
    • 4.1.1 Port Address

      46
    • 4.1.2 Port Addressing Exceptions

      47
    • 4.1.3 Memory and I/O Mapping

      47
      • 4.1.3.1 Memory Routing and Translation

        47
      • 4.1.3.2 I/O Routing and Translation

        49
      • 4.1.3.3 Special Cycles

        49
  • 4.2 GLIU Register Descriptions

    50
    • 4.2.1 Standard GeodeLink™ Device (GLD) MSRs

      55
      • 4.2.1.1 GLD Capabilities MSR (GLD_MSR_CAP)

        55
      • 4.2.1.2 GLD Master Configuration MSR (GLD_MSR_CONFIG)

        55
      • 4.2.1.3 GLD SMI MSR (GLD_MSR_SMI)

        56
      • 4.2.1.4 GLD Error MSR (GLD_MSR_ERROR)

        57
      • 4.2.1.5 GLD Power Management MSR (GLD_MSR_PM)

        59
      • 4.2.1.6 GLD Diagnostic MSR (GLD_MSR_DIAG)

        60
    • 4.2.2 GLIU Specific Registers

      60
      • 4.2.2.1 Coherency (COH)

        60
      • 4.2.2.2 Port Active Enable (PAE)

        61
      • 4.2.2.3 Arbitration (ARB)

        62
      • 4.2.2.4 Asynchronous SMI (ASMI)

        62
      • 4.2.2.5 Asynchronous ERR (AERR)

        63
      • 4.2.2.6 GLIU Physical Capabilities (PHY_CAP)

        65
      • 4.2.2.7 N Outstanding Response (NOUT_RESP)

        66
      • 4.2.2.8 N Outstanding Write Data (NOUT_WDATA)

        67
      • 4.2.2.9 SLAVE_ONLY

        67
      • 4.2.2.10 WHO AM I (WHOAMI)

        68
      • 4.2.2.11 GLIU Slave Disable (GLIU_SLV)

        69
      • 4.2.2.12 Arbitration2 (ARB2)

        70
    • 4.2.3 GLIU Statistic and Comparator MSRs

      71
      • 4.2.3.1 Descriptor Statistic Counter (STATISTIC_CNT[0:3])

        71
      • 4.2.3.2 Statistic Mask (STATISTIC_MASK[0:3]

        72
      • 4.2.3.3 Statistic Action (STATISTIC_ACTION[0:3]

        73
      • 4.2.3.4 Request Compare Value (RQ_COMPARE_VAL[0:3]

        74
      • 4.2.3.5 Request Compare Mask (RQ_COMPARE_MASK[0:3]

        75
      • 4.2.3.6 DA Compare Value Low (DA_COMPARE_VAL_LO[0:3]

        76
      • 4.2.3.7 DA Compare Value High (DA_COMPARE_VAL_HI[0:3]

        77
      • 4.2.3.8 DA Compare Mask Low (DA_COMPARE_MASK_LO[0:3])

        78
      • 4.2.3.9 DA Compare Mask High (DA_COMPARE_MASK_HI[0:3])

        79
    • 4.2.4 P2D Descriptor Registers

      80
      • 4.2.4.1 P2D Base Mask Descriptor (P2D_BM)

        80
      • 4.2.4.2 P2D Base Mask Offset Descriptor (P2D_BMO)

        81
      • 4.2.4.3 P2D Range Descriptor (P2D_R)

        82
      • 4.2.4.4 P2D Range Offset Descriptor (P2D_RO)

        83
      • 4.2.4.5 P2D Swiss Cheese Descriptor (P2D_SC)

        84
    • 4.2.5 SPARE MSRs (SPARE_MSR[0:9], A:F)

      85
    • 4.2.6 I/O Descriptors

      86
      • 4.2.6.1 IOD Base Mask Descriptors (IOD_BM)

        86
      • 4.2.6.2 IOD Swiss Cheese Descriptors (IOD_SC)

        87
• CPU Core

  89
  • 5.1 Core Processor Initialization

    89
  • 5.2 Instruction Set Overview

    90
    • 5.2.1 Lock Prefix

      90
    • 5.2.2 Register Sets

      90
  • 5.3 Application Register Set

    91
    • 5.3.1 General Purpose Registers

      92
    • 5.3.2 Segment Registers

      92
    • 5.3.3 Instruction Pointer Register

      92
    • 5.3.4 EFLAGS Register

      93
  • 5.4 System Register Set

    94
    • 5.4.1 Control Registers

      95
  • 5.5 CPU Core Register Descriptions

    99
    • 5.5.1 Standard GeodeLink™ Device MSRs

      108
      • 5.5.1.1 GLD Capabilities MSR (GLD_MSR_CAP)

        108
      • 5.5.1.2 GLD Master Configuration MSR (GLD_MSR_CONFIG)

        108
      • 5.5.1.3 GLD SMI MSR (GLD_MSR_SMI)

        109
      • 5.5.1.4 GLD Error MSR (GLD_MSR_ERROR)

        109
      • 5.5.1.5 GLD Power Management MSR (GLD_MSR_PM)

        109
      • 5.5.1.6 GLD Diagnostic Bus Control MSR (GLD_MSR_DIAG)

        109
    • 5.5.2 CPU Core Specific MSRs

      110
      • 5.5.2.1 Time Stamp Counter MSR (TSC_MSR)

        110
      • 5.5.2.2 Performance Event Counter 0 MSR (PERF_CNT0_MSR)

        110
      • 5.5.2.3 Performance Event Counter 1 MSR (PERF_CNT1_MSR)

        111
      • 5.5.2.4 SYSENTER/SYSEXIT Code Segment Selector MSR (SYS_CS_MSR)

        112
      • 5.5.2.5 SYSENTER/SYSEXIT Stack Pointer MSR (SYS_SP_MSR)

        113
      • 5.5.2.6 SYSENTER/SYSEXIT Instruction Pointer MSR (SYS_IP_MSR)

        113
      • 5.5.2.7 Performance Event Counter 0 Select MSR (PERF_SEL0_MSR

        114
      • 5.5.2.8 Performance Event Counter 1 Select MSR (PERF_SEL1_MSR)

        114
      • 5.5.2.9 Instruction Fetch Configuration MSR (IF_CONFIG_MSR)

        115
      • 5.5.2.10 IF Invalidate MSR (IF_INVALIDATE_MSR)

        118
      • 5.5.2.11 IF Test Address MSR (IF_TEST_ADDR_MSR)

        118
      • 5.5.2.12 IF Test Data MSR (IF_TEST_DATA_MSR)

        119
      • 5.5.2.13 IF Sequential Count MRS (IF_SEQCOUNT_MSR)

        122
      • 5.5.2.14 IF Built-In Self-Test MSR (IF_BIST_MSR)

        123
      • 5.5.2.15 Exception Unit (XC) Configuration MSR (XC_CONFIG_MSR)

        124
      • 5.5.2.16 XC Mode MSR (XC_MODE_MSR)

        125
      • 5.5.2.17 XC History MSR (XC_HIST_MSR)

        126
      • 5.5.2.18 XC Microcode Address MSR (XC_UADDR_MSR)

        127
      • 5.5.2.19 ID Configuration MSR (ID_CONFIG_MSR)

        127
      • 5.5.2.20 SMM Control MSR (SMM_CTL_MSR)

        128
      • 5.5.2.21 Debug Management Interrupt (DMI) Control Register

        129
      • 5.5.2.22 Temporary MSRs

        130
      • 5.5.2.23 Segment Selector/Flags MSRs

        131
      • 5.5.2.24 SMM Header MSR (SMM_HDR_MSR)

        132
      • 5.5.2.25 DMM Header MSR (DMM_HDR_MSR)

        133
      • 5.5.2.26 Segment Base/Limit MSRs

        134
      • 5.5.2.27 Debug Registers 1 and 0 MSR (DR1_DR0_MSR)

        135
      • 5.5.2.28 Debug Registers 3 and 2 MSR (DR3_DR2_MSR)

        135
      • 5.5.2.29 Debug Registers 7 and 6 MSR (DR6_DR7_MSR)

        136
      • 5.5.2.30 Extended Debug Registers 1 and 0 MSR (XDR1_XDR0_MSR)

        137
      • 5.5.2.31 Extended Debug Registers 3 and 2 MSR (XDR3_XDR2_MSR)

        137
      • 5.5.2.32 Extended Debug Registers 5 and 4 MSR (XDR5_XDR4_MSR)

        138
      • 5.5.2.33 Extended Debug Registers 7 and 6 MSR (XDR7_XDR6_MSR)

        138
      • 5.5.2.34 Extended Debug Registers 9 and 8 MSR (XDR9_XDR8_MSR)

        140
      • 5.5.2.35 Extended Debug Registers 11 and 10 MSR (XDR11_XDR10_MSR)

        141
      • 5.5.2.36 EX Stage Instruction Pointer MSR (EX_IP_MSR)

        141
      • 5.5.2.37 WB Stage Instruction Pointer MSR (WB_IP_MSR)

        142
      • 5.5.2.38 EX Stage Linear Instruction Pointer MSR (EX_LIP_MSR)

        142
      • 5.5.2.39 WB Stage Linear Instruction Pointer MSR (WB_LIP_MSR)

        143
      • 5.5.2.40 C1/C0 Linear Instruction Pointer MSR (C1_C0_LIP_MSR)

        143
      • 5.5.2.41 C3/C2 Linear Instruction Pointer MSR (C3_C2_LIP_MSR)

        144
      • 5.5.2.42 Floating Point Environment Code Segment (FPENV_CS_MSR)

        144
      • 5.5.2.43 Floating Point Environment Instruction Pointer (FPENV_IP_MSR)

        145
      • 5.5.2.44 Floating Point Environment Data Segment (FPENV_DS_MSR)

        145
      • 5.5.2.45 Floating Point Environment Data Pointer (FPENV_DP_MSR)

        146
      • 5.5.2.46 Floating Point Environment Opcode Pointer (FPENV_OP_MSR)

        146
      • 5.5.2.47 Address Calculation Unit Configuration MSR (AC_CONFIG_MSR)

        147
      • 5.5.2.48 General Register MSRs

        148
      • 5.5.2.49 Extended Flags MSR (EFLAG_MSR)

        149
      • 5.5.2.50 Control Register 0 MSR (CR0_MSR)

        149
      • 5.5.2.51 Instruction Memory Configuration MSR (IM_CONFIG_MSR)

        150
      • 5.5.2.52 Instruction Cache Index MSR (IC_INDEX_MSR)

        152
      • 5.5.2.53 Instruction Cache Data MSR (IC_DATA_MSR)

        152
      • 5.5.2.54 Instruction Cache Tag (IC_TAG_MSR)

        153
      • 5.5.2.55 Instruction Cache Tag with Increment (IC_TAG_I_MSR)

        154
      • 5.5.2.56 L0 Instruction Cache Data MSR (L0_IC_DATA_MSR)

        154
      • 5.5.2.57 L0 Instruction Cache Tag with Increment MSR (L0_IC_TAG_I_MSR)

        154
      • 5.5.2.58 L1 Instruction TLB Index (ITB_INDEX_MSR)

        155
      • 5.5.2.59 L1 Instruction TLB Least Recently Used MSR (ITB_LRU_MSR)

        156
      • 5.5.2.60 L1 Instruction TLB Entry MSRs

        157
      • 5.5.2.61 Instruction Memory Subsystem BIST Tag MSR (IM_BIST_TAG_MSR)

        158
      • 5.5.2.62 Instruction Memory Subsystem BIST Data MSR (IM_BIST_DATA_MSR)

        158
      • 5.5.2.63 Data Memory Subsystem Configuration 0 MSR (DM_CONFIG0_MSR)

        159
      • 5.5.2.64 Data Memory Subsystem Configuration 1 MSR (DM_CONFIG1_MSR)

        162
      • 5.5.2.65 Data Memory Subsystem Prefetch Lock MSR (DM_PFLOCK_MSR)

        163
      • 5.5.2.66 Default Region Configuration Properties MSR (RCONF_DEFAULT_MSR)

        164
      • 5.5.2.67 Region Configuration Bypass MSR (RCONF_BYPASS_MSR)

        165
      • 5.5.2.68 Region Configuration A0000-BFFFF MSR (RCONF_A0_BF_MSR)

        165
      • 5.5.2.69 Region Configuration C0000-DFFFF MSR (RCONF_C0_DF_MSR)

        166
      • 5.5.2.70 Region Configuration E0000-FFFFF MSR (RCONF_E0_FF_MSR)

        166
      • 5.5.2.71 Region Configuration SMM MSR (RCONF_SMM_MSR)

        167
      • 5.5.2.72 Region Configuration DMM MSR (RCONF_DMM_MSR)

        168
      • 5.5.2.73 Region Configuration Range MSRs 0 through 7

        169
      • 5.5.2.74 x86 Control Registers MSRs (CR1, CR2, CR3, CR4)

        172
      • 5.5.2.75 Data Cache Index MSR (DC_INDEX_MSR)

        172
      • 5.5.2.76 Data Cache Data MSR (DC_DATA_MSR)

        173
      • 5.5.2.77 Data Cache Tag MSR (DC_TAG_MSR)

        173
      • 5.5.2.78 Data Cache Tag with Increment MSR (DC_TAG_I_MSR)

        174
      • 5.5.2.79 Data/Instruction Cache Snoop Register (SNOOP_MSR)

        175
      • 5.5.2.80 L1 Data TLB Index Register (L1DTLB_INDEX_MSR)

        175
      • 5.5.2.81 L1 Data TLB Least Recently Used MSR (L1DTLB_LRU_MSR)

        176
      • 5.5.2.82 L1 Data TLB Entry MSR (L1DTLB_ENTRY_MSR)

        177
      • 5.5.2.83 L1 Data TLB Entry with Increment MSR (L1DTLB_ENTRY_I_MSR)

        178
      • 5.5.2.84 L2 TLB/DTE/PTE Index MSR (L2TLB_INDEX_MSR)

        178
      • 5.5.2.85 L2 TLB/DTE/PTE Least Recently Used MSR (L2TLB_LRU_MSR)

        179
      • 5.5.2.86 L2 TLB/DTE/PTE Entry MSR (L2TLB_ENTRY_MSR)

        180
      • 5.5.2.87 L2 TLB/DTE/PTE Entry with Increment MSR (L2TLB_ENTRY_I_MSR)

        182
      • 5.5.2.88 Data Memory Subsystem Built-In Self-Test MSR (DM_BIST_MSR)

        182
      • 5.5.2.89 Bus Controller Configuration 0 MSR (BC_CONFIG0_MSR)

        183
      • 5.5.2.90 Bus Controller Configuration 1 MSR (BC_CONFIG1_MSR)

        184
      • 5.5.2.91 Reserved Status MSR (RSVD_STS_MSR)

        185
      • 5.5.2.92 MSR Lock MSR (MSR_LOCK_MSR)

        185
      • 5.5.2.93 Real Time Stamp Counter MSR (RTSC_MSR)

        186
      • 5.5.2.94 TSC and RTSC Low DWORDs MSR (RTSC_TSC_MSR)

        186
      • 5.5.2.95 L2 Cache Configuration MSR (L2_CONFIG_MSR)

        187
      • 5.5.2.96 L2 Cache Status MSR (L2_STATUS_MSR)

        188
      • 5.5.2.97 L2 Cache Index MSR (L2_INDEX_MSR)

        188
      • 5.5.2.98 L2 Cache Data MSR (L2_DATA_MSR)

        189
      • 5.5.2.99 L2 Cache Tag MSR (L2_TAG_MSR)

        189
      • 5.5.2.100 L2 Cache Tag with Increment MSR (L2_TAG_I_MSR)

        190
      • 5.5.2.101 L2 Cache Built-In Self-Test MSR (L2_BIST_MSR)

        190
      • 5.5.2.102 L2 Cache Treatment Control MSR (L2_TRTMNT_CTL_MSR)

        192
      • 5.5.2.103 Power Mode MSR (PMODE_MSR)

        193
      • 5.5.2.104 Bus Controller Extended Debug Registers 1 and 0 MSR (BXDR1_BXDR0_MSR)

        194
      • 5.5.2.105 Bus Controller Extended Debug Registers 3 and 2 MSR (BXDR3_BXDR2_MSR)

        194
      • 5.5.2.106 Bus Controller Extended Debug Registers 6 and 7 MSR (BXDR6_BXDR7_MSR)

        195
      • 5.5.2.107 Bus Controller Debug Registers 0 through 3 MSRs

        197
      • 5.5.2.108 Bus Controller Debug Register 6 MSR (BDR6_MSR)

        198
      • 5.5.2.109 Bus Controller Debug Register 7 MSR (BDR7_MSR)

        198
      • 5.5.2.110 Memory Subsystem Array Control Enable MSR (MSS_ARRAY_CTL_EN_MSR)

        200
      • 5.5.2.111 Memory Subsystem Array Control 0 MSR (MSS_ARRAY_CTL0_MSR)

        200
      • 5.5.2.112 Memory Subsystem Array Control 1 MSR (MSS_ARRAY_CTL1_MSR)

        201
      • 5.5.2.113 Memory Subsystem Array Control 2 MSR (MSS_ARRAY_CTL2_MSR)

        201
      • 5.5.2.114 FPU Modes MSR (FP_MODE_MSR)

        202
      • 5.5.2.115 FPU Reserved MSR (FPU_RSVD_MSR)

        202
      • 5.5.2.116 FPU Reserved MSR (FPU_RSVD_MSR)

        202
      • 5.5.2.117 FPU x87 Control Word MSR (FPU_CW_MSR)

        203
      • 5.5.2.118 FPU x87 Status Word MSR (FPU_SW_MSR)

        203
      • 5.5.2.119 FPU x87 Tag Word MSR (FPU_TW_MSR)

        203
      • 5.5.2.120 FPU Busy MSR (FPU_BUSY_MSR)

        204
      • 5.5.2.121 FPU Register Map MSR (FPU_MAP_MSR)

        204
      • 5.5.2.122 Mantissa of Rx MSRs

        205
      • 5.5.2.123 Exponent of Rx MSRs

        206
      • 5.5.2.124 FPU Reserved MSRs (FPU_RSVD_MSR)

        207
      • 5.5.2.125 CPU ID MSRs

        207
• Integrated Functions

  209
  • 6.1 GeodeLink™ Memory Controller

    210
    • 6.1.1 Functional Hardware

      211
      • 6.1.1.1 Address Translation

        211
      • 6.1.1.2 Arbitration

        215
      • 6.1.1.3 Data Path

        216
      • 6.1.1.4 GLMC/GLCP/Pad Delay Control Settings

        216
      • 6.1.1.5 Basic Timing Diagrams

        216
    • 6.1.2 Power Control

      218
      • 6.1.2.1 Entry into PMode1 (Save-to-RAM)

        218
      • 6.1.2.2 Resume from PMode1

        218
    • 6.1.3 BIOS Initialization Sequence

      218
  • 6.2 GeodeLink™ Memory Controller Register Descriptions

    219
    • 6.2.1 Standard GeodeLink™ Device (GLD) MSRs

      220
      • 6.2.1.1 GLD Capabilities MSR (GLD_MSR_CAP)

        220
      • 6.2.1.2 GLD Master Configuration MSR (GLD_MSR_CONFIG) - Not Used

        220
      • 6.2.1.3 GLD SMI MSR (GLD_MSR_SMI)

        220
      • 6.2.1.4 GLD Error MSR (GLD_MSR_ERROR)

        221
      • 6.2.1.5 GLD Power Management (GLD_MSR_PM)

        222
      • 6.2.1.6 GLD Diagnostic (GLD_MSR_DIAG)

        222
    • 6.2.2 GLMC Specific MSRs

      223
      • 6.2.2.1 Row Addresses Bank0 DIMM0, Bank1 DIMM0 (MC_CF_BANK01)

        223
      • 6.2.2.2 Row Addresses Bank2 DIMM0, Bank3 DIMM0 (MC_CF_BANK23)

        223
      • 6.2.2.3 Row Addresses Bank4 DIMM0, Bank5 DIMM0 (MC_CF_BANK45)

        224
      • 6.2.2.4 Row Addresses Bank6 DIMM0, Bank7 DIMM0 (MC_CF_BANK67)

        224
      • 6.2.2.5 Row Addresses Bank0 DIMM1, Bank1 DIMM0 (MC_CF_BANK89)

        225
      • 6.2.2.6 Row Addresses Bank2 DIMM1, Bank3 DIMM1 (MC_CF_BANKAB)

        225
      • 6.2.2.7 Row Addresses Bank4 DIMM1, Bank5 DIMM1 (MC_CF_BANKCD)

        226
      • 6.2.2.8 Row Addresses Bank6 DIMM1, Bank7 DIMM1 (MC_CF_BANKEF)

        226
      • 6.2.2.9 Refresh and SDRAM Program (MC_CF07_DATA)

        227
      • 6.2.2.10 Timing and Mode Program (MC_CF8F_DATA)

        229
      • 6.2.2.11 Feature Enables (MC_CF1017_DATA)

        231
      • 6.2.2.12 Performance Counters (MC_CFPERF_CNT1)

        232
      • 6.2.2.13 Counter and CAS Control (MC_PERCNT2)

        233
      • 6.2.2.14 Clocking and Debug (MC_CFCLK_DBUG)

        233
      • 6.2.2.15 Page Open Status (MC_CFPG_OPEN)

        235
      • 6.2.2.16 Reserved Register

        235
      • 6.2.2.17 PM Sensitivity Counters (MC_CF_PMCTR)

        236
  • 6.3 Graphics Processor

    237
    • 6.3.1 Command Buffer

      239
    • 6.3.2 Channel 3

      241
      • 6.3.2.1 Rotating BLTs

        242
      • 6.3.2.2 Rotating Video

        242
      • 6.3.2.3 Color Depth Conversion

        242
      • 6.3.2.4 Palletized Color Support

        243
      • 6.3.2.5 Anti-Aliased Text Support

        244
      • 6.3.2.6 8x8 Color Pattern

        244
      • 6.3.2.7 Patterned Vectors

        244
      • 6.3.2.8 Channel 3 Host Source

        245
      • 6.3.2.9 Channel 3 Hints

        245
    • 6.3.3 BLT Operation

      245
    • 6.3.4 Vector Operation

      246
    • 6.3.5 Pipelined Operation

      246
    • 6.3.6 Pattern Generation

      246
      • 6.3.6.1 Monochrome Patterns

        246
      • 6.3.6.2 Color Patterns

        247
    • 6.3.7 8x8 Color Patterns

      249
    • 6.3.8 Source Data

      249
      • 6.3.8.1 Source Data Formats

        249
      • 6.3.8.2 Host Source

        250
      • 6.3.8.3 Source Expansion

        251
      • 6.3.8.4 Source Transparency

        251
    • 6.3.9 Destination Data

      251
    • 6.3.10 Raster Operations (ROP)

      251
    • 6.3.11 Image Compositing Using Alpha

      252
  • 6.4 Graphics Processor Register Definitions

    254
    • 6.4.1 Standard GeodeLink™ Device (GLD) MSRs

      256
      • 6.4.1.1 GLD Capabilities MSR (GLD_MSR_CAP)

        256
      • 6.4.1.2 GLD Master Configuration MSR (GLD_MSR_CONFIG)

        256
      • 6.4.1.3 GLD SMI MSR (GLD_MSR_SMI)

        257
      • 6.4.1.4 GLD Error MSR (GLD_MSR_ERROR)

        257
      • 6.4.1.5 GLD Power Management MSR (GLD_MSR_PM)

        258
      • 6.4.1.6 GLD Diagnostic MSR (GLD_MSR_DIAG)

        258
    • 6.4.2 Graphics Processor Configuration Registers

      259
      • 6.4.2.1 Destination Offset (GP_DST_OFFSET)

        259
      • 6.4.2.2 Source Offset (GP_SRC_OFFSET)

        259
      • 6.4.2.3 Vector Error (GP_VEC_ERR)

        260
      • 6.4.2.4 Stride (GP_STRIDE)

        260
      • 6.4.2.5 BLT Width/Height (GP_WID_HEIGHT)

        261
      • 6.4.2.6 Vector Length (GP_VEC_LEN)

        261
      • 6.4.2.7 Source Color Foreground (GP_SRC_COLOR_FG)

        262
      • 6.4.2.8 Source Color Background (GP_SRC_COLOR_BG)

        263
      • 6.4.2.9 Pattern Color (GP_PAT_COLOR_x)

        264
      • 6.4.2.10 Pattern Data (GP_PAT_DATA_x)

        265
      • 6.4.2.11 Raster Mode (GP_RASTER_MODE)

        265
      • 6.4.2.12 Vector Mode (GP_VECTOR_MODE)

        267
      • 6.4.2.13 BLT Mode (GP_BLT_MODE)

        268
      • 6.4.2.14 Status and Reset (GP_BLT_STATUS, GP_RESET)

        269
      • 6.4.2.15 Host Source (GP_HST_SRC)

        269
      • 6.4.2.16 Base Offset (GP_BASE_OFFSET)

        270
      • 6.4.2.17 Command Top (GP_CMD_TOP)

        270
      • 6.4.2.18 Command Bottom (GP_CMD_BOT)

        271
      • 6.4.2.19 Command Read (GP_CMD_READ)

        271
      • 6.4.2.20 Command Write (GP_CMD_WRITE)

        272
      • 6.4.2.21 Offset (GP_CH3_OFFSET)

        272
      • 6.4.2.22 Stride (GP_CH3_MODE_STR)

        273
      • 6.4.2.23 Width/Height (GP_CH3_WIDHI)

        275
      • 6.4.2.24 Host Source (GP_CH3_HSRC)

        275
      • 6.4.2.25 LUT Index (GP_LUT_INDEX)

        276
      • 6.4.2.26 LUT Data (GP_LUT_DATA)

        276
      • 6.4.2.27 Interrupt Control (GP_INT_CNTRL)

        277
  • 6.5 Display Controller

    278
    • 6.5.1 GUI Functional Overview

      281
      • 6.5.1.1 Display Mode Support

        281
      • 6.5.1.2 Display FIFO

        283
      • 6.5.1.3 Hardware Cursor and Icon Overlays

        283
      • 6.5.1.4 Display Refresh Compression

        285
      • 6.5.1.5 Dirty/Valid RAM

        285
      • 6.5.1.6 Palette/Gamma RAM

        285
      • 6.5.1.7 Display Address Generator

        285
      • 6.5.1.8 Display Timing Generator

        285
      • 6.5.1.9 Video Overlay Support

        286
      • 6.5.1.10 Output Formats

        287
    • 6.5.2 VBI Data

      287
    • 6.5.3 GenLock

      287
    • 6.5.4 VGA Block Functional Overview

      288
      • 6.5.4.1 VGA Modes

        288
      • 6.5.5.2 Graphics Controller

        289
      • 6.5.5.3 Write Modes

        290
      • 6.5.5.4 Read Modes

        291
    • 6.5.6 Graphics Scaler/Filter

      293
    • 6.5.7 Color Key Elimination

      296
    • 6.5.8 Using the Graphics Filter

      296
    • 6.5.9 Interlaced Modes

      297
    • 6.5.10 Interlaced Timing Examples

      298
  • 6.6 Display Controller Register Descriptions

    300
    • 6.6.1 Standard GeodeLink™ Device (GLD) Registers (MSRs)

      305
      • 6.6.1.1 GLD Capabilities MSR (GLD_MSR_CAP)

        305
      • 6.6.1.2 GLD Master Configuration MSR (GLD_MSR_CONFIG)

        305
      • 6.6.1.3 GLIU0 Device SMI MSR (GLD_MSR_SMI)

        306
      • 6.6.1.4 GLD Error MSR (GLD_MSR_ERROR)

        308
      • 6.6.1.5 GLD Power Management MSR (GLD_MSR_PM)

        310
      • 6.6.1.6 GLIU0 Device Diagnostic MSR (GLD_MSR_DIAG)

        310
    • 6.6.2 Display Controller Specific MSRs

      311
      • 6.6.2.1 SPARE MSR

        311
      • 6.6.2.2 DC RAM Control MSR (DC_RAM_CTL_MSR)

        311
    • 6.6.3 Configuration and Status Registers

      312
      • 6.6.3.1 DC Unlock (DC_UNLOCK)

        312
      • 6.6.3.2 DC General Configuration (DC_GENERAL_CFG)

        314
      • 6.6.3.3 DC Display Configuration (DC_DISPLAY_CFG)

        317
      • 6.6.3.4 DC Arbitration Configuration (DC_ARB_CFG)

        319
    • 6.6.4 Memory Organization Registers

      321
      • 6.6.4.1 DC Frame Buffer Start Address (DC_FB_ST_OFFSET)

        321
      • 6.6.4.2 DC Compression Buffer Start Address (DC_CB_ST_OFFSET)

        322
      • 6.6.4.3 DC Cursor Buffer Start Address (DC_CURS_ST_OFFSET)

        322
      • 6.6.4.4 DC Video Y Buffer Start Address Offset (DC_VID_Y_ST_OFFSET)

        323
      • 6.6.4.5 DC Video U Buffer Start Address Offset (DC_VID_U_ST_OFFSET)

        323
      • 6.6.4.6 DC Video V Buffer Start Address Offset (DC_VID_V_ST_OFFSET)

        324
      • 6.6.4.7 DC Dirty/Valid Region Top (DC_DV_TOP)

        324
      • 6.6.4.8 DC Line Size (DC_LINE_SIZE)

        325
      • 6.6.4.9 DC Graphics Pitch (DC_GFX_PITCH)

        326
      • 6.6.4.10 DC Video YUV Pitch (DC_VID_YUV_PITCH)

        326
    • 6.6.5 Timing Registers

      327
      • 6.6.5.1 DC Horizontal and Total Timing (DC_H_ACTIVE_TIMING)

        328
      • 6.6.5.2 DC CRT Horizontal Blanking Timing (DC_H_BLANK_TIMING)

        329
      • 6.6.5.3 DC CRT Horizontal Sync Timing (DC_H_SYNC_TIMING)

        329
      • 6.6.5.4 DC Vertical and Total Timing (DC_V_ACTIVE_TIMING)

        330
      • 6.6.5.5 DC CRT Vertical Blank Timing (DC_V_BLANK_TIMING)

        331
      • 6.6.5.6 DC CRT Vertical Sync Timing (DC_V_SYNC_TIMING)

        331
      • 6.6.5.7 DC Frame Buffer Active Region Register (DC_FB_ACTIVE)

        332
    • 6.6.6 Cursor Position and Line Count/Status Registers

      332
      • 6.6.6.1 DC Cursor X Position (DC_CURSOR_X)

        332
      • 6.6.6.2 DC Cursor Y Position (DC_CURSOR_Y)

        333
      • 6.6.6.3 DC Line Count/Status (DC_LINE_CNT/STATUS)

        333
    • 6.6.7 Palette Access FIFO Diagnostic Registers

      335
      • 6.6.7.1 DC Palette Address (DC_PAL_ADDRESS)

        335
      • 6.6.7.2 DC Palette Data (DC_PAL_DATA)

        336
      • 6.6.7.3 DC Display FIFO Diagnostic (DC_DFIFO_DIAG)

        336
      • 6.6.7.4 DC Compression FIFO Diagnostic (DC_CFIFO_DIAG)

        337
    • 6.6.8 Video Downscaling

      338
      • 6.6.8.1 DC Video Downscaling Delta (DC_VID_DS_DELTA)

        338
    • 6.6.9 GLIU Control Registers

      339
      • 6.6.9.1 DC GLIU0 Memory Offset (DC_GLIU0_MEM_OFFSET)

        339
      • 6.6.9.2 DC Dirty/Valid RAM Control (DC_DV_CTL)

        339
      • 6.6.9.3 DC Dirty/Valid RAM Access (DC_DV_ACCESS)

        340
    • 6.6.10 Graphics Scaling Control Registers

      341
      • 6.6.10.1 DC Graphics Filter Scale (DC_GFX_SCALE)

        341
      • 6.6.10.2 DC IRQ/Filter Control (DC_IRQ_FILT_CTL)

        342
      • 6.6.10.3 DC Filter Coefficient Data Register 1 (DC_FILT_COEFF1)

        343
      • 6.6.10.4 DC Filter Coefficient Data Register 2 (DC_FILT_COEFF2)

        344
    • 6.6.11 VBI Control Registers

      344
      • 6.6.11.1 DC VBI Even Control (DC_VBI_EVEN_CTL)

        344
      • 6.6.11.2 DC VBI Odd Control (DC_VBI_ODD_CTL)

        345
      • 6.6.11.3 DC VBI Horizontal Control (DC_VBI_HOR)

        345
      • 6.6.11.4 DC VBI Odd Line Enable (DC_VBI_LN_ODD)

        346
      • 6.6.11.5 DC VBI Even Line Enable (DC_VBI_LN_EVEN)

        346
      • 6.6.11.6 DC VBI Pitch and Size (DC_VBI_PITCH)

        347
    • 6.6.12 Color Key Control Registers

      347
      • 6.6.12.1 DC Color Key (DC_CLR_KEY)

        347
      • 6.6.12.2 DC Color Key Mask (DC_CLR_KEY_MASK)

        348
      • 6.6.12.3 DC Color Key Horizontal Position (DC_CLR_KEY_X)

        348
      • 6.6.12.4 DC Color Key Vertical Position (DC_CLR_KEY_Y)

        348
      • 6.6.12.5 DC Interrupt (DC_IRQ)

        349
    • 6.6.13 Interrupt and GenLock Registers

      350
      • 6.6.13.1 DC GenLock Control (DC_GENLK_CTL)

        350
    • 6.6.14 Even Field Video Address Registers

      351
      • 6.6.14.1 DC Even Field Video Y Start Address Offset (DC_VID_EVEN_Y_ST_OFFSET)

        351
      • 6.6.14.2 DC Even Field Video U Start Address Offset (DC_VID_EVEN_U_ST_OFFSET)

        352
      • 6.6.14.3 DC Even Field Video V Start Address Offset (DC_VID_EVEN_V_ST_OFFSET)

        352
    • 6.6.15 Even Field Vertical Timing Registers

      353
      • 6.6.15.1 DC Vertical and Total Timing for Even Fields (DC_V_ACTIVE_EVEN_TIMING)

        353
      • 6.6.15.2 DC CRT Vertical Blank Timing for Even Fields (DC_V_BLANK_EVEN_TIMING)

        354
      • 6.6.15.3 DC CRT Vertical Sync Timing for Even Fields (DC_V_SYNC_EVEN_TIMING)

        354
    • 6.6.16 VGA Block Configuration Registers

      355
      • 6.6.16.1 VGA Configuration (VGA_CONFIG)

        355
      • 6.6.16.2 VGA Status (VGA_STATUS)

        355
    • 6.6.17 VGA Block Standard Registers

      356
      • 6.6.17.1 VGA Miscellaneous Output

        356
      • 6.6.17.2 VGA Input Status Register 0

        357
      • 6.6.17.3 VGA Input Status Register 1

        357
      • 6.6.17.4 VGA Feature Control

        357
    • 6.6.18 VGA Sequencer Registers

      358
      • 6.6.18.1 VGA Sequencer Index

        358
      • 6.6.18.2 VGA Sequencer Data

        358
      • 6.6.18.3 VGA Reset

        358
      • 6.6.18.4 VGA Clocking Mode

        359
      • 6.6.18.5 VGA Map Mask

        359
      • 6.6.18.6 VGA Character Map Select

        360
      • 6.6.18.7 VGA Memory Mode

        360
    • 6.6.19 VGA CRT Controller Registers

      361
      • 6.6.19.1 CRTC Index

        362
      • 6.6.19.2 CRTC Data

        363
      • 6.6.19.3 Horizontal Total

        363
      • 6.6.19.4 Horizontal Display Enable End

        363
      • 6.6.19.5 Horizontal Blank Start

        363
      • 6.6.19.6 Horizontal Blank End

        364
      • 6.6.19.7 Horizontal Sync Start

        364
      • 6.6.19.8 Horizontal Sync End

        364
      • 6.6.19.9 Vertical Total

        365
      • 6.6.19.10 Overflow

        365
      • 6.6.19.11 Preset Row Scan

        365
      • 6.6.19.12 Maximum Scan Line

        366
      • 6.6.19.13 Cursor Start

        366
      • 6.6.19.14 Cursor End

        367
      • 6.6.19.15 Start Address High

        367
      • 6.6.19.16 Start Address Low

        367
      • 6.6.19.17 Cursor Location High

        367
      • 6.6.19.18 Cursor Location Low

        368
      • 6.6.19.19 Vertical Sync Start

        368
      • 6.6.19.20 Vertical Sync End

        368
      • 6.6.19.21 Vertical Display Enable End

        369
      • 6.6.19.22 Offset

        369
      • 6.6.19.23 Underline Location

        369
      • 6.6.19.24 Vertical Blank Start

        370
      • 6.6.19.25 Vertical Blank End

        370
      • 6.6.19.26 CRTC Mode Control

        370
      • 6.6.19.27 Line Compare

        372
      • 6.6.19.28 CPU Data Latch State

        372
      • 6.6.19.29 Attribute Index/Data FF State

        372
      • 6.6.19.30 Attribute Index State

        373
    • 6.6.20 VGA Graphics Controller Registers

      373
      • 6.6.20.1 VGA Graphics Controller Index

        373
      • 6.6.20.2 VGA Graphics Controller Data

        374
      • 6.6.20.3 VGA Set/Reset

        374
      • 6.6.20.4 VGA Enable Set/Reset

        374
      • 6.6.20.5 VGA Color Compare

        375
      • 6.6.20.6 VGA Data Rotate

        375
      • 6.6.20.7 VGA Read Map Select

        376
      • 6.6.20.8 VGA Graphics Mode

        376
      • 6.6.20.9 VGA Miscellaneous

        377
      • 6.6.20.10 VGA Color Don’t Care

        378
      • 6.6.20.11 VGA Bit Mask

        378
    • 6.6.21 Attribute Controller Registers

      378
      • 6.6.21.1 Attribute Controller Index/Data

        379
      • 6.6.21.2 EGA Palette

        379
      • 6.6.21.3 Attribute Mode Control

        380
      • 6.6.21.4 Overscan Color

        380
      • 6.6.21.5 Color Plane Enable

        381
      • 6.6.21.6 Horizontal Pel Panning

        381
      • 6.6.21.7 Color Select

        382
    • 6.6.22 Video DAC Registers

      382
      • 6.6.22.1 Video DAC Palette Address

        383
      • 6.6.22.2 Video DAC State

        383
      • 6.6.22.3 Video DAC Palette Data

        383
      • 6.6.22.4 Video DAC Palette Mask

        384
    • 6.6.23 VGA Block Extended Registers

      384
      • 6.6.23.1 ExtendedRegisterLock

        385
      • 6.6.23.2 ExtendedModeControl

        385
      • 6.6.23.3 ExtendedStartAddress

        385
      • 6.6.23.4 WriteMemoryAperture

        386
      • 6.6.23.5 ReadMemoryAperture

        386
      • 6.6.23.6 BlinkCounterCtl

        386
      • 6.6.23.7 BlinkCounter

        387
      • 6.6.23.8 VGALatchSavRes

        387
      • 6.6.23.9 DACIFSavRes

        387
  • 6.7 Video Processor

    388
    • 6.7.1 Architecture Overview

      388
    • 6.7.2 Functional Description

      390
      • 6.7.2.1 Video Formatter

        391
      • 6.7.2.2 4x4 Filter/Scaler

        391
      • 6.7.2.3 Horizontal Downscaling

        392
    • 6.7.3 X and Y Upscaler

      393
    • 6.7.4 Color Space Converter

      393
    • 6.7.5 Video Overlay

      394
      • 6.7.5.1 Alpha-Blending

        394
      • 6.7.5.2 Gamma RAM

        397
      • 6.7.5.3 Video Processor Module Display Interface

        397
      • 6.7.5.4 Video Interface

        397
    • 6.7.6 Video Output Port

      398
      • 6.7.6.1 Functional Overview

        398
      • 6.7.6.2 Supported Features

        398
      • 6.7.6.3 HBLANK and VBLANK Signals

        399
      • 6.7.6.4 Interface to Video Processor

        401
      • 6.7.6.5 Operating Modes

        402
      • 6.7.6.6 New VIP 2.0 Video Flags

        404
      • 6.7.6.7 BT.601 Support

        404
      • 6.7.6.8 VIP 2.0 Level System

        404
      • 6.7.6.9 VBI Data

        404
    • 6.7.7 Flat Panel Display Controller

      405
      • 6.7.7.1 FP Functional Overview

        405
      • 6.7.7.2 FP Architecture Overview

        405
      • 6.7.7.3 FP Functional Description

        406
    • 6.7.8 VP Resolution Table

      411
    • 6.7.9 Display RGB Modes

      411
  • 6.8 Video Processor Register Descriptions

    412
    • 6.8.1 Standard GeodeLink™ Device MSRs

      415
      • 6.8.1.1 GLD Capabilities MSR (GLD_MSR_CAP)

        415
      • 6.8.1.2 GLD Master Configuration MSR (GLD_MSR_CONFIG)

        415
      • 6.8.1.3 GLD SMI MSR (GLD_MSR_SMI)

        417
      • 6.8.1.4 GLD Error MSR (GLD_MSR_ERROR)

        417
      • 6.8.1.5 GLD Power Management MSR (GLD_MSR_PM)

        418
      • 6.8.1.6 GLD Diagnostic MSR (GLD_MSR_DIAG)

        418
    • 6.8.2 Video Processor Module Specific MSRs

      419
      • 6.8.2.1 VP Diagnostic MSR (MSR_DIAG_VP)

        419
      • 6.8.2.2 Pad Select MSR (MSR_PADSEL)

        420
    • 6.8.3 Video Processor Module Control/Configuration Registers

      421
      • 6.8.3.1 Video Configuration (VCFG)

        421
      • 6.8.3.2 Display Configuration (DCFG)

        422
      • 6.8.3.3 Video X Position (VX)

        424
      • 6.8.3.4 Video Y Position (VY)

        425
      • 6.8.3.5 Video Scale (SCL)

        425
      • 6.8.3.6 Video Color Key Register (VCK)

        426
      • 6.8.3.7 Video Color Mask (VCM)

        427
      • 6.8.3.8 Palette Address (PAR)

        428
      • 6.8.3.9 Palette Data (PDR)

        428
      • 6.8.3.10 Saturation Scale (SLR)

        429
      • 6.8.3.11 Miscellaneous (MISC)

        430
      • 6.8.3.12 CRT Clock Select (CCS)

        431
      • 6.8.3.13 Video Y Scale (VYS)

        431
      • 6.8.3.14 Video X Scale (VXS)

        431
      • 6.8.3.15 Video Downscaler Control (VDC)

        432
      • 6.8.3.16 CRC Signature (CRC)

        433
      • 6.8.3.17 32-Bit CRC Signature (CRC32)

        434
      • 6.8.3.18 Video De-Interlacing and Alpha Control (VDE)

        434
      • 6.8.3.19 Cursor Color Key (CCK)

        436
      • 6.8.3.20 Cursor Color Mask (CCM)

        437
      • 6.8.3.21 Cursor Color 1 (CC1)

        437
      • 6.8.3.22 Cursor Color 2 (CC2)

        438
      • 6.8.3.23 Alpha Window 1 X Position (A1X)

        438
      • 6.8.3.24 Alpha Window 1 Y Position (A1Y)

        439
      • 6.8.3.25 Alpha Window 1 Color (A1C)

        439
      • 6.8.3.26 Alpha Window 1 Control (A1T)

        440
      • 6.8.3.27 Alpha Window 2 X Position (A2X)

        441
      • 6.8.3.28 Alpha Window 2 Y Position (A2Y)

        442
      • 6.8.3.29 Alpha Window 2 Color (AC2)

        442
      • 6.8.3.30 Alpha Window 2 Control (A2T)

        443
      • 6.8.3.31 Alpha Window 3 X Position (A3X)

        444
      • 6.8.3.32 Alpha Window 3 Y Position (A3Y)

        445
      • 6.8.3.33 Alpha Window 3 Color (A3C)

        445
      • 6.8.3.34 Alpha Window 3 Control (A3T)

        446
      • 6.8.3.35 Video Request (VRR)

        447
      • 6.8.3.36 Alpha Watch (AWT)

        448
      • 6.8.3.37 Video Processor Test Mode (VTM)

        448
      • 6.8.3.38 Even Video Y Position (VYE)

        449
      • 6.8.3.39 Even Alpha Window 1 Y Position (A1YE)

        449
      • 6.8.3.40 Even Alpha Window 2 Y Position (A2YE)

        450
      • 6.8.3.41 Even Alpha Window 3 Y Position (A3YE)

        450
      • 6.8.3.42 Video Coefficient RAM (VCR)

        451
      • 6.8.3.43 Panel Timing Register 1 (PT1)

        451
      • 6.8.3.44 Panel Timing Register 2 (PT2)

        453
      • 6.8.3.45 Power Management (PM)

        454
      • 6.8.3.46 Dither and Frame Rate Control (DFC)

        456
      • 6.8.3.47 Dither RAM Control and Address (DCA)

        457
      • 6.8.3.48 Dither Memory Data (DMD)

        458
      • 6.8.3.49 Panel CRC Signature (CRC)

        458
      • 6.8.3.50 32-Bit Panel CRC (CRC32)

        459
      • 6.8.3.51 Video Output Port Configuration (VOP_CONFIG)

        459
      • 6.8.3.52 Video Output Port Signature (VOP_SIG)

        461
  • 6.9 Video Input Port

    462
    • 6.9.1 Features

      462
      • 6.9.1.1 Performance Metrics

        462
    • 6.9.2 VIP Block Descriptions

      463
      • 6.9.2.1 Input Formatter

        464
      • 6.9.2.2 Input Control

        464
      • 6.9.2.3 VIP Capture RAM

        464
      • 6.9.2.4 VIP Register Block

        464
      • 6.9.2.5 GLIU Interface

        464
    • 6.9.3 Functional Description

      465
    • 6.9.4 VIP Operation Modes

      465
    • 6.9.5 Mode 1a,b,c - VIP Input Data (simplified BT.656)

      466
      • 6.9.5.1 SAV/EAV Packets

        466
      • 6.9.5.2 Ancillary Packets

        469
    • 6.9.6 Message Passing Mode

      470
    • 6.9.7 Data Streaming Mode

      470
    • 6.9.8 BT.601 Mode

      471
    • 6.9.9 YUV 4:2:2 to YUV 4:2:0 Translation

      473
    • 6.9.10 Software Model

      475
      • 6.9.10.1 Video Data Buffers

        476
      • 6.9.10.2 VBI Data Buffers

        476
      • 6.9.10.3 Ancillary Data Buffers

        476
      • 6.9.10.4 Message Passing/Data Streaming Modes

        476
    • 6.9.11 Bob and Weave

      480
      • 6.9.11.1 Bob

        480
      • 6.9.11.2 Weave

        480
    • 6.9.12 VIP Interrupts

      480
    • 6.9.13 VIP Input Video Status

      481
  • 6.10 Video Input Port Register Descriptions

    482
    • 6.10.1 Standard GeodeLink™ Device (GLD) MSRs

      484
      • 6.10.1.1 GLD Capabilities MSR (GLD_MSR_CAP)

        484
      • 6.10.1.2 GLD Configuration MSR (GLD_MSR_CONFIG)

        484
      • 6.10.1.3 GLD SMI MSR (GLD_MSR_SMI)

        485
      • 6.10.1.4 GLD Error MSR (GLD_MSR_ERROR)

        486
      • 6.10.1.5 GLD Power Management Register (GLD_MSR_PM)

        487
      • 6.10.1.6 GLD Diagnostic MSR (GLD_MSR_DIAG)

        487
    • 6.10.2 VIP Control/Configuration Registers

      488
      • 6.10.2.1 VIP Control Register 1 (VIP_CTL_REG1)

        488
      • 6.10.2.2 VIP Control Register 2 (VIP_CTL_REG2)

        490
      • 6.10.2.3 VIP Status (VIP_STATUS)

        492
      • 6.10.2.4 VIP Interrupt (VIP_INT)

        494
      • 6.10.2.5 VIP Current/Target (VIP_CUR_TAR)

        495
      • 6.10.2.6 VIP Max Address (VIP_MAX_ADDR)

        495
      • 6.10.2.7 VIP Task A Video Even Base Address (VIP_TASK_A_VID_EVEN_BASE)

        496
      • 6.10.2.8 VIP Task A Video Odd Base Address (VIP_TASK_A_VID_ODD_BASE)

        496
      • 6.10.2.9 VIP Task A VBI Even Base Address (VIP_TASK_A_VBI_EVEN_BASE)

        497
      • 6.10.2.10 VIP Task A VBI Odd Base Address (VIP_TASK_A_VBI_ODD_BASE)

        497
      • 6.10.2.11 VIP Task A Video Pitch (VIP_TASK_A_VID_PITCH)

        498
      • 6.10.2.12 VIP Control Register 3 (VIP_CONTRL_REG3)

        498
      • 6.10.2.13 VIP Task A V Offset (VIP_TASK_A_V_OFFSET)

        499
      • 6.10.2.14 VIP Task A U Offset (VIP_TASK_A_U_OFFSET)

        500
      • 6.10.2.15 VIP Task B Video Even Base/Horizontal End (VIP_TASK_B_VID_EVEN_BASE_HORIZ_END)

        500
      • 6.10.2.16 VIP Task B Video Odd Base/Horizontal Start (VIP_TASK_B_VID_ODD_BASE_HORIZ_START)

        501
      • 6.10.2.17 VIP Task B VBI Even Base/VBI End (VIP_TASK_B_VBI_EVEN_BASE_VBI_END)

        501
      • 6.10.2.18 VIP Task B VBI Odd Base/VBI Start (VIP_TASK_B_VBI_ODD_BASE_VBI_START)

        502
      • 6.10.2.19 VIP Task B Data Pitch/Vertical Start Even (VIP_TASK_B_DATA_PITCH_VERT_START_EVEN)

        502
      • 6.10.2.20 VIP Task B V Offset (VIP_TASK_B_V_Offset)

        503
      • 6.10.2.21 VIP Task B U Offset (VIP_TASK_B_U_OFFSET)

        504
      • 6.10.2.22 VIP Ancillary Data/Message Passing/Data Streaming Buffer1 Base Address (VIP_ANC_MSG_1_BASE)

        504
      • 6.10.2.23 VIP Ancillary Data/Message Passing/Data Streaming Buffer 2 Base Address (VIP_ANC_MSG_2_BASE)

        505
      • 6.10.2.24 VIP Ancillary Data/Message Passing/Data Streaming Buffer Size (VIP_ANC_MSG_SIZE)

        505
      • 6.10.2.25 VIP Page Offset/ Page Count (VIP_PAGE_OFFSET)

        506
      • 6.10.2.26 VIP Vertical Start/Stop (VIP_VERT_START_STOP)

        506
      • 6.10.2.27 VIP FIFO Address (VIP_FIFO_R_W_ADDR)

        507
      • 6.10.2.28 VIP FIFO Data (VIP_FIFO_DATA)

        507
      • 6.10.2.29 VIP VSYNC Error Count (VIP_SYNC_ERR_COUNT)

        508
      • 6.10.2.30 VIP Task A U Even Offset (VIP_TASK_A_U_EVEN_OFFSET)

        508
      • 6.10.2.31 VIP Task A V Even Offset (VIP_TASK_A_V_EVEN_OFFSET)

        509
  • 6.11 Security Block

    510
    • 6.11.1 Security Block Features

      510
      • 6.11.1.1 Performance Metrics

        510
    • 6.11.2 Functional Description

      511
      • 6.11.2.1 EEPROM ID Interface

        512
      • 6.11.2.2 Security Block Interrupts

        512
      • 6.11.2.3 GLIU Interface

        512
  • 6.12 Security Block Register Descriptions

    513
    • 6.12.1 Standard GeodeLink™ (GLD) Device MSRs

      515
      • 6.12.1.1 GLD Capabilities MSR (GLD_MSR_CAP)

        515
      • 6.12.1.2 GLD Master Configuration MSR (GLD_MSR_CONFIG)

        515
      • 6.12.1.3 GLD SMI MSR (GLD_MSR_SMI)

        516
      • 6.12.1.4 GLD Error MSR (GLD_MSR_ERROR)

        516
      • 6.12.1.5 GLD Power Management MSR (GLD_MSR_PM)

        518
      • 6.12.1.6 GLD Diagnostic MSR (GLD_MSR_DIAG)

        518
    • 6.12.2 Security Block Specific MSRs

      519
      • 6.12.2.1 GLD Control MSR (GLD_MSR_CTRL)

        519
    • 6.12.3 Security Block Configuration/Control Registers

      520
      • 6.12.3.1 SB Control A (SB_CTL_A)

        520
      • 6.12.3.2 SB Control B (SB_CTL_B)

        521
      • 6.12.3.3 SB AES Interrupt (SB_AES_INT)

        522
      • 6.12.3.4 SB Source A (SB_SOURCE_A)

        522
      • 6.12.3.5 SB Destination A (SB_DEST_A)

        523
      • 6.12.3.6 SB Length A (SB_LENGTH_A)

        523
      • 6.12.3.7 SB Source B (SB_SOURCE_B)

        524
      • 6.12.3.8 SB Destination B (SB_DEST_B)

        524
      • 6.12.3.9 SB Length B (SB_LENGTH_B)

        525
      • 6.12.3.10 SB Writable Key 0 (SB_WKEY_0)

        525
      • 6.12.3.11 SB Writable Key 1 (SB_WKEY_1)

        526
      • 6.12.3.12 SB Writable Key 2 (SB_WKEY_2)

        526
      • 6.12.3.13 SB Writable Key 3 (SB_WKEY_3)

        527
      • 6.12.3.14 SB CBC Initialization Vector 0 (SB_CBC_IV_0)

        527
      • 6.12.3.15 SB CBC Initialization Vector 1 (SB_CBC_IV_1)

        528
      • 6.12.3.16 SB CBC Initialization Vector 2 (SB_CBC_IV_2)

        528
      • 6.12.3.17 SB CBC Initialization Vector 3 (SB_CBC_IV_3)

        528
      • 6.12.3.18 SB Random Number (SB_RANDOM_NUM)

        529
      • 6.12.3.19 SB Random Number Status (SB_RANDOM_NUM_STATUS)

        529
      • 6.12.3.20 SB EEPROM Command (SB_EEPROM_COMM)

        530
      • 6.12.3.21 SB EEPROM Address (SB_EEPROM_ADDR)

        531
      • 6.12.3.22 SB EEPROM Data (SB_EEPROM_DATA)

        531
      • 6.12.3.23 SB EEPROM Security State (SB_EEPROM_SEC_STATE)

        532
  • 6.13 GeodeLink™ Control Processor

    533
    • 6.13.1 TAP Controller

      533
    • 6.13.2 Reset Logic

      535
    • 6.13.3 Clock Control

      535
      • 6.13.3.1 Power Management

        535
    • 6.13.4 Companion Device Interface

      536
      • 6.13.4.1 GIO_GLIU

        536
      • 6.13.4.2 GIO_SYNC

        536
      • 6.13.4.3 GIO_PCI

        536
  • 6.14 GeodeLink™ Control Processor Register Descriptions

    539
    • 6.14.1 Standard GeodeLink™ Device MSRs

      541
      • 6.14.1.1 GLD Capabilities MSR (GLD_MSR_CAP)

        541
      • 6.14.1.2 GLD Master Configuration MSR (GLD_MSR_CONFIG)

        541
      • 6.14.1.3 GLD SMI MSR (GLD_MSR_SMI)

        542
      • 6.14.1.4 GLD Error MSR (GLD_MSR_ERROR)

        543
      • 6.14.1.5 GLD Power Management MSR (GLD_MSR_PM)

        544
      • 6.14.1.6 GLD Diagnostic MSR (GLD_MSR_DIAG)

        544
    • 6.14.2 GLCP Specific MSRs - GLCP Control MSRs

      545
      • 6.14.2.1 GLCP Clock Disable Delay Value (GLCP_CLK_DIS_DELAY)

        545
      • 6.14.2.2 GLCP Clock Mask for Sleep Request (GLCP_PMCLKDISABLE)

        545
      • 6.14.2.3 Chip Fabrication Information (GLCP_FAB)

        547
      • 6.14.2.4 GLCP Global Power Management Controls (GLCP_GLB_PM)

        547
      • 6.14.2.5 GLCP Debug Output from Chip (GLCP_DBGOUT)

        548
      • 6.14.2.6 GLCP Processor Status (GLCP_PROCSTAT)

        548
      • 6.14.2.7 GLCP DOWSER (GLCP_DOWSER)

        549
      • 6.14.2.8 GLCP I/O Delay Controls (GLCP_DELAY_CONTROLS)

        549
      • 6.14.2.9 GLCP Clock Control (GLCP_CLKOFF)

        551
      • 6.14.2.10 GLCP Clock Active (GLCP_CLKACTIVE)

        552
      • 6.14.2.11 GLCP Clock Mask for Debug Clock Stop Action (GLCP_CLKDISABLE)

        553
      • 6.14.2.12 GLCP Clock Active Mask for Suspend Acknowledge (GLCP_CLK4ACK)

        553
      • 6.14.2.13 GLCP System Reset and PLL Control (GLCP_SYS_RSTPLL)

        554
      • 6.14.2.14 GLCP Dot Clock PLL Control (GLCP_DOTPLL)

        557
      • 6.14.2.15 GLCP Debug Clock Control (GLCP_DBGCLKCTL)

        559
      • 6.14.2.16 Chip Revision ID (GLCP_CHIP_REVID)

        559
      • 6.14.2.17 GLCP Control (GLCP_CNT)

        560
      • 6.14.2.18 GLCP Level 2 (GLCP_LVL2)

        560
      • 6.14.2.19 GLCP Throttle or C2 Start Delay (GLCP_TH_SD)

        561
      • 6.14.2.20 GLCP Scale Factor (GLCP_TH_SF)

        561
      • 6.14.2.21 GLCP Processor Throttle Off Delay (GLCP_TH_OD)

        562
    • 6.14.3 GLCP IGNNE I/Os

      562
    • 6.14.4 GLCP Specific MSRs - GLCP Debug Interface MSRs

      563
      • 6.14.4.1 GLCP DAC (GLCP_DAC)

        563
    • 6.14.5 GLCP Specific MSRs - GLCP Companion Device Interface MSRs

      564
      • 6.14.5.1 CPU A20M Signal (MSR_A20M)

        564
      • 6.14.5.2 CPU INIT Signal (MSR_INIT)

        564
      • 6.14.5.3 GLIU Device Interrupt Status (MSR_INTAX)

        565
  • 6.15 GeodeLink™ PCI Bridge

    566
    • 6.15.1 GeodeLink™ Interface Block

      567
    • 6.15.2 FIFO/Synchronization Block

      567
    • 6.15.3 Transaction Forwarding Block

      567
      • 6.15.3.1 Atomic External MSR Access

        567
    • 6.15.4 PCI Bus Interface Block

      569
      • 6.15.4.1 PCI Configuration and Virtual PCI Header Support

        569
    • 6.15.5 PCI Arbiter

      570
    • 6.15.6 Exception Handling

      571
      • 6.15.6.1 Out-Bound Write Exceptions

        571
      • 6.15.6.2 Out-Bound Read Exceptions

        571
      • 6.15.6.3 In-Bound Write Exceptions

        571
      • 6.15.6.4 In-Bound Read Exceptions

        571
  • 6.16 GeodeLink™ PCI Bridge Register Descriptions

    572
    • 6.16.1 Standard GeodeLink™ Device (GLD) MSRs

      574
      • 6.16.1.1 GLD Capabilities MSR (GLD_MSR_CAP)

        574
      • 6.16.1.2 GLD Master Configuration MSR (GLD_MSR_CONFIG)

        574
      • 6.16.1.3 GLD SMI MSR (GLD_MSR_SMI)

        575
      • 6.16.1.4 GLD Error MSR (GLD_MSR_ERROR)

        576
      • 6.16.1.5 GLD Power Management MSR (GLD_MSR_PM)

        577
      • 6.16.1.6 GLD Diagnostic MSR (GLD_MSR_DIAG)

        577
    • 6.16.2 GLPCI Specific Registers

      578
      • 6.16.2.1 GLPCI Global Control (GLPCI_CTRL)

        578
      • 6.16.2.2 GLPCI Arbiter Control (GLPCI_ARB)

        581
      • 6.16.2.3 GLPCI VPH / PCI Configuration Cycle Control (GLPCI_PBUS)

        584
      • 6.16.2.4 GLPCI Debug Packet Configuration (GLPCI_DEBUG)

        584
      • 6.16.2.5 GLPCI Fixed Region Enables (GLPCI_REN)

        584
      • 6.16.2.6 GLPCI Fixed Region Configuration A0-BF (GLPCI_A0)

        585
      • 6.16.2.7 GLPCI Fixed Region Configuration C0-DF (GLPCI_C0)

        586
      • 6.16.2.8 GLPCI Fixed Region Configuration E0-FF (GLPCI_E0)

        587
      • 6.16.2.9 GLPCI Memory Region 0 Configuration (GLPCI_R0)

        588
      • 6.16.2.10 GLPCI Memory Region 1 Configuration (GLPCI_R1)

        589
      • 6.16.2.11 GLPCI Memory Region 2 Configuration (GLPCI_R2)

        590
      • 6.16.2.12 GLCPI Memory Region 3 Configuration (GLPCI_R3)

        591
      • 6.16.2.13 GLCPI Memory Region 4 Configuration (GLPCI_R4)

        592
      • 6.16.2.14 GLPCI Memory Region 5 Configuration (GLPCI_R5)

        593
      • 6.16.2.15 GLPCI External MSR Access Configuration (GLPCI EXT_MSR)

        594
      • 6.16.2.16 GLPCI Spare

        595
      • 6.16.2.17 GLPCI General Purpose I/O (GLPCI_GPIO)

        596
• Electrical Specifications

  597
  • 7.1 Electrical Connections

    597
    • 7.1.1 PWR/GND Connections and Decoupling

      597
    • 7.1.2 NC-Designated Balls

      597
    • 7.1.3 Unused Inputs

      597
  • 7.2 Absolute Maximum Ratings

    597
  • 7.3 Operating Conditions

    598
  • 7.4 DC Current

    599
    • 7.4.1 Power State Parameter Definitions

      599
    • 7.4.2 Definition and Measurement Techniques of Current Parameters

      599
    • 7.4.3 DC Current Measurements

      599
  • 7.5 DC Characteristics

    604
  • 7.6 AC Characteristics

    607
• Instruction Set

  619
  • 8.1 General Instruction Set Format

    619
    • 8.1.1 Prefix (Optional)

      620
    • 8.1.2 Opcode

      621
      • 8.1.2.1 w Field (Operand Size)

        621
      • 8.1.2.2 d Field (Operand Direction)

        621
      • 8.1.2.3 s Field (Immediate Data Field Size)

        621
      • 8.1.2.4 eee Field (MOV-Instruction Register Selection)

        622
    • 8.1.3 mod and r/m Byte (Memory Addressing)

      622
    • 8.1.4 reg Field

      624
      • 8.1.4.1 sreg2 Field (ES, CS, SS, DS Register Selection)

        624
      • 8.1.4.2 sreg3 Field (FS and GS Segment Register Selection)

        624
    • 8.1.5 s-i-b Byte (Scale, Indexing, Base)

      625
      • 8.1.5.1 ss Field (Scale Selection)

        625
      • 8.1.5.2 Index Field (Index Selection)

        625
      • 8.1.5.3 Base Field (s-i-b Present)

        626
  • 8.2 CPUID Instruction Set

    627
    • 8.2.1 Standard CPUID Levels

      627
      • 8.2.1.1 CPUID Instruction with EAX = 00000000h

        627
      • 8.2.1.2 CPUID Instruction with EAX = 00000001h

        627
    • 8.2.2 Extended CPUID Levels

      629
      • 8.2.2.1 CPUID Instruction with EAX = 80000000h

        629
      • 8.2.2.2 CPUID Instruction with EAX = 80000001h

        629
      • 8.2.2.3 CPUID Instruction with EAX = 80000002h, 80000003h, or 80000004h

        631
      • 8.2.2.4 CPUID Instruction with EAX = 80000005h

        632
      • 8.2.2.5 CPUID Instruction with EAX = 80000006h

        632
  • 8.3 Processor Core Instruction Set

    633
    • 8.3.1 Opcodes

      633
    • 8.3.2 Clock Counts

      633
    • 8.3.3 Flags

      633
    • 8.3.4 Non-Standard Processor Core Instructions

      646
      • 8.3.4.1 DMINT - Enter Debug Management Mode

        646
      • 8.3.4.2 ICEBP - Call Debug Exception Handler

        647
      • 8.3.4.3 MOV - Move to/from Test Registers

        648
      • 8.3.4.4 RDM - Leave Debug Management Mode

        649
      • 8.3.4.5 RSDC - Restore Segment Register and Descriptor

        650
      • 8.3.4.6 RSLDT - Restore Local Descriptor Table Register and Descriptor

        651
      • 8.3.4.7 RSM - Leave System Management Mode

        652
      • 8.3.4.8 RSTS - Restore Task Register and Descriptor

        653
      • 8.3.4.9 SETALC - Set AL to CF

        653
      • 8.3.4.10 SMINT - Enter System Management Mode

        654
      • 8.3.4.11 Exceptions

        655
      • 8.3.4.12 SVDC - Save Segment Register and Descriptor

        656
      • 8.3.4.13 SVLDT - Save Local Descriptor Table Register and Descriptor

        656
      • 8.3.4.14 SVTS - Save Task Register and Descriptor

        657
  • 8.4 MMX™, FPU, and AMD 3DNow!™ Technology Instructions Sets

    658
    • 8.4.1 Non-Standard AMD 3DNow!™ Technology Instructions

      674
      • 8.4.1.1 PFRCPV - Floating-Point Reciprocal Approximation

        674
      • 8.4.1.2 PFRSQRTV - Floating-Point Reciprocal Square Root Approximation

        674
• Package Specifications

  675
  • 9.1 Physical Dimensions

    675
• Support Documentation

  677
  • A.1 Order Information

    677
  • A.2 Data Book Revision History

    679