Manuels d'utilisation pour Analog Devices AD9609 Evaluation Board AD9609-40EBZ

Table des matières

• FEATURES

  1
• APPLICATIONS

  1
• FUNCTIONAL BLOCK DIAGRAM

  1
• PRODUCT HIGHLIGHTS

  1
• TABLE OF CONTENTS

  2
• REVISION HISTORY

  2
• GENERAL DESCRIPTION

  3
• SPECIFICATIONS

  4
  • DC SPECIFICATIONS

    4
  • AC SPECIFICATIONS

    5
  • DIGITAL SPECIFICATIONS

    6
  • SWITCHING SPECIFICATIONS

    7
  • TIMING SPECIFICATIONS

    8
• ABSOLUTE MAXIMUM RATINGS

  9
  • THERMAL CHARACTERISTICS

    9
  • ESD CAUTION

    9
• PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

  10
• TYPICAL PERFORMANCE CHARACTERISTICS

  11
  • AD9609-80

    11
  • AD9609-65

    13
  • AD9609-40

    14
  • AD9609-20

    15
• EQUIVALENT CIRCUITS

  16
• THEORY OF OPERATION

  17
  • ANALOG INPUT CONSIDERATIONS

    17
    • Input Common Mode

      17
    • Differential Input Configurations

      18
    • Single-Ended Input Configuration

      18
  • VOLTAGE REFERENCE

    19
    • Internal Reference Connection

      19
    • External Reference Operation

      19
  • CLOCK INPUT CONSIDERATIONS

    20
    • Clock Input Options

      20
    • Input Clock Divider

      20
    • Clock Duty Cycle

      21
    • Jitter Considerations

      21
  • POWER DISSIPATION AND STANDBY MODE

    22
  • DIGITAL OUTPUTS

    22
    • Digital Output Enable Function (OEB)

      22
  • TIMING

    23
    • Data Clock Output (DCO)

      23
• BUILT-IN SELF-TEST (BIST) AND OUTPUT TEST

  24
  • BUILT-IN SELF-TEST (BIST)

    24
  • OUTPUT TEST MODES

    24
• SERIAL PORT INTERFACE (SPI)

  25
  • CONFIGURATION USING THE SPI

    25
  • HARDWARE INTERFACE

    26
  • CONFIGURATION WITHOUT THE SPI

    26
  • SPI ACCESSIBLE FEATURES

    26
• MEMORY MAP

  27
  • READING THE MEMORY MAP REGISTER TABLE

    27
  • OPEN LOCATIONS

    27
  • DEFAULT VALUES

    27
    • Logic Levels

      27
    • Transfer Register Map

      27
  • MEMORY MAP REGISTER TABLE

    28
  • MEMORY MAP REGISTER DESCRIPTIONS

    30
    • USR2 (Register 0x101)

      30
    • Bit 3—Enable GCLK Detect

      30
    • Bit 2—Run GCLK

      30
    • Bit 0—Disable SDIO Pull-Down

      30
• APPLICATIONS INFORMATION

  31
  • DESIGN GUIDELINES

    31
    • Power and Ground Recommendations

      31
    • Exposed Paddle Thermal Heat Sink Recommendations

      31
    • VCM

      31
    • RBIAS

      31
    • Reference Decoupling

      31
    • SPI Port

      31
• OUTLINE DIMENSIONS

  32
  • ORDERING GUIDE

    32