Manuels d'utilisation pour Cisco Xeon E7520

Table des matières

• 1 Introduction

  9
  • 1.1 Terminology

    9
  • 1.2 References

    11
  • 1.3 State of Data

    11
• 2 Electrical Specifications

  13
  • 2.1 Processor Maximum Ratings

    13
  • 2.2 Socket Voltage Identification

    14
  • 2.3 Signal Groups

    20
  • 2.4 Processor DC Specifications

    21
  • 2.5 Intel® QPI and Intel® SMI Interface Differential Signaling

    26
    • 2.5.1 Intel® QPI Signaling Specifications

      27
    • 2.5.2 Intel® QPI Electrical Specifications

      31
    • 2.5.3 Intel® SMI Signaling Specifications

      35
    • 2.5.4 Intel® SMI Transmitter and Receiver Specifications

      35
  • 2.6 Platform Environmental Control Interface (PECI) DC Specifications

    42
    • 2.6.1 DC Characteristics

      42
    • 2.6.2 Input Device Hysteresis

      42
  • 2.7 DC Specifications

    43
  • 2.8 AC Specifications

    44
  • 2.9 Processor AC Timing Waveforms

    50
  • 2.10 Flexible Motherboard Guidelines

    56
  • 2.11 Reserved (RSVD) or Unused Signals

    56
  • 2.12 Test Access Port Connection

    56
  • 2.13 Mixing Processors

    56
  • 2.14 Processor SPD Interface

    56
• 3 Processor Package Mechanical Specifications

  57
  • 3.1 Package Mechanical Specifications

    57
    • 3.1.1 Package Mechanical Drawing

      58
    • 3.1.2 Processor Component Keep-Out Zones

      61
    • 3.1.3 Package Loading Specifications

      61
    • 3.1.4 Package Handling Guidelines

      61
    • 3.1.5 Package Insertion Specifications

      61
    • 3.1.6 Processor Mass Specification

      62
    • 3.1.7 Processor Materials

      62
    • 3.1.8 Processor Markings

      62
    • 3.1.9 Processor Land Coordinates

      63
• 4 Land Listing

  65
  • 4.1 Intel® Xeon® Processor 7500 Series Package Bottom Pin Assignments

    65
    • 4.1.1 Intel® Xeon® Processor 7500 Series Pin List, Sorted by Land Name

      65
    • 4.1.2 Intel® Xeon® Processor 7500 Series Pin List, Sorted by Land Number

      85
• 5 Signal Definitions

  105
• 6 Thermal Specifications

  111
  • 6.1 Package Thermal Specifications

    111
    • 6.1.1 Thermal Specifications

      111
    • 6.1.2 Thermal Metrology

      117
  • 6.2 Processor Thermal Features

    118
    • 6.2.1 Thermal Monitor Features

      118
    • 6.2.2 Intel® Thermal Monitor 1

      118
    • 6.2.3 Intel® Thermal Monitor 2

      118
    • 6.2.4 On-Demand Mode

      119
    • 6.2.5 PROCHOT_N Signal

      120
    • 6.2.6 FORCE_PR_N Signal

      120
    • 6.2.7 THERMTRIP_N Signal

      121
    • 6.2.8 THERMALERT_N Signal

      121
  • 6.3 Platform Environment Control Interface (PECI)

    121
    • 6.3.1 PECI Client Capabilities

      122
    • 6.3.2 Client Command Suite

      123
    • 6.3.3 Multi-Domain Commands

      139
    • 6.3.4 Client Responses

      139
    • 6.3.5 Originator Responses

      140
    • 6.3.6 Temperature Data

      141
    • 6.3.7 Client Management

      142
• 7 Features

  145
  • 7.1 Introduction

    145
  • 7.2 Clock Control and Low Power States

    146
    • 7.2.1 Intel® Xeon® Processor 7500 Series C-State Power Specifications

      146
  • 7.3 Sideband Access to Processor Information ROM via SMBus

    146
    • 7.3.1 Processor Information ROM

      146
    • 7.3.2 Scratch EEPROM

      148
    • 7.3.3 PIROM and Scratch EEPROM Supported SMBus Transactions

      149
  • 7.4 SMBus Memory Component Addressing

    149
  • 7.5 Managing Data in the PIROM

    150
    • 7.5.1 Header

      150
    • 7.5.2 Processor Data

      154
    • 7.5.3 Processor Core Data

      156
    • 7.5.4 Processor Uncore Data

      159
    • 7.5.5 Package Data

      164
    • 7.5.6 Part Number Data

      165
    • 7.5.7 Thermal Reference Data

      167
    • 7.5.8 Feature Data

      169
    • 7.5.9 Other Data

      171
    • 7.5.10 Checksums

      172