Manuel D’UtilisationTable des matièresFeatures1Configurations1Functional Description1Selection Guide1Logic Block Diagram (CY7C1317CV18)2Logic Block Diagram (CY7C1917CV18)2Logic Block Diagram (CY7C1319CV18)3Logic Block Diagram (CY7C1321CV18)3Pin Configuration4165-Ball FBGA (13 x 15 x 1.4 mm) Pinout4Pin Definitions6Functional Overview8Read Operations8Write Operations8Byte Write Operations8Single Clock Mode8DDR Operation8Depth Expansion9Programmable Impedance9Echo Clocks9DLL9Application Example10Truth Table10Burst Address Table (CY7C1319CV18, CY7C1321CV18)11Write Cycle Descriptions11Write Cycle Descriptions11Write Cycle Descriptions12IEEE 1149.1 Serial Boundary Scan (JTAG)13Disabling the JTAG Feature13Test Access Port-Test Clock13Test Mode Select (TMS)13Test Data-In (TDI)13Test Data-Out (TDO)13Performing a TAP Reset13TAP Registers13Instruction Register13Bypass Register13Boundary Scan Register13Identification (ID) Register13TAP Instruction Set13IDCODE14SAMPLE Z14SAMPLE/PRELOAD14BYPASS14EXTEST14EXTEST OUTPUT BUS TRI-STATE14Reserved14TAP Controller State Diagram15TAP Controller Block Diagram16TAP Electrical Characteristics16TAP AC Switching Characteristics17TAP Timing and Test Conditions17Identification Register Definitions18Scan Register Sizes18Instruction Codes18Boundary Scan Order19Power Up Sequence in DDR-II SRAM20Power Up Sequence20DLL Constraints20Maximum Ratings21Operating Range21Electrical Characteristics21DC Electrical Characteristics21AC Electrical Characteristics22Capacitance23Thermal Resistance23Switching Characteristics24Switching Waveforms26Ordering Information27Package Diagram30Document History Page31Sales, Solutions, and Legal Information31Worldwide Sales and Design Support31Products31PSoC Solutions31Taille: 720 koPages: 31Language: EnglishOuvrir le manuel