Manuel D’UtilisationTable des matièresFeatures1Configurations1Functional Description1Logic Block Diagram (CY7C1510KV18)2Logic Block Diagram (CY7C1525KV18)2Logic Block Diagram (CY7C1512KV18)3Logic Block Diagram (CY7C1514KV18)3Pin Configuration4165-Ball FBGA (13 x 15 x 1.4 mm) Pinout4Pin Definitions6Functional Overview8Read Operations8Write Operations8Byte Write Operations8Single Clock Mode8Concurrent Transactions8Depth Expansion8Programmable Impedance8Echo Clocks9PLL9Application Example9Truth Table10Write Cycle Descriptions10Write Cycle Descriptions11Write Cycle Descriptions11IEEE 1149.1 Serial Boundary Scan (JTAG)12Disabling the JTAG Feature12Test Access Port-Test Clock12Test Mode Select (TMS)12Test Data-In (TDI)12Test Data-Out (TDO)12Performing a TAP Reset12TAP Registers12Instruction Register12Bypass Register12Boundary Scan Register12Identification (ID) Register12TAP Instruction Set12IDCODE13SAMPLE Z13SAMPLE/PRELOAD13BYPASS13EXTEST13EXTEST OUTPUT BUS TRISTATE13Reserved13TAP Controller State Diagram14TAP Controller Block Diagram15TAP Electrical Characteristics15TAP AC Switching Characteristics16TAP Timing and Test Conditions16Identification Register Definitions17Scan Register Sizes17Instruction Codes17Boundary Scan Order18Power Up Sequence in QDR-II SRAM19Power Up Sequence19PLL Constraints19Maximum Ratings20Operating Range20Electrical Characteristics20DC Electrical Characteristics20AC Electrical Characteristics21Capacitance22Thermal Resistance22Switching Characteristics23Switching Waveforms25Ordering Information26Package Diagram29Document History Page30Sales, Solutions, and Legal Information30Worldwide Sales and Design Support30Products30PSoC Solutions30Taille: 830 koPages: 30Language: EnglishOuvrir le manuel