Manuel D’UtilisationTable des matièresFeatures1Configurations1Functional Description1Selection Guide1Logic Block Diagram (CY7C1546V18)2Logic Block Diagram (CY7C1557V18)2Logic Block Diagram (CY7C1548V18)3Logic Block Diagram (CY7C1550V18)3Pin Configuration4165-Ball FBGA (15 x 17 x 1.4 mm) Pinout4Pin Definitions6Functional Overview8Read Operations8Write Operations8Byte Write Operations8Double Date Rate Operation8Depth Expansion8Programmable Impedance8Echo Clocks9Valid Data Indicator (QVLD)9DLL9Application Example9Truth Table10Write Cycle Descriptions10Write Cycle Descriptions11Write Cycle Descriptions11IEEE 1149.1 Serial Boundary Scan (JTAG)12Disabling the JTAG Feature12Test Access Port-Test Clock12Test Mode Select (TMS)12Test Data-In (TDI)12Test Data-Out (TDO)12Performing a TAP Reset12TAP Registers12Instruction Register12Bypass Register12Boundary Scan Register12Identification (ID) Register12TAP Instruction Set12IDCODE13SAMPLE Z13SAMPLE/PRELOAD13BYPASS13EXTEST13EXTEST OUTPUT BUS TRI-STATE13Reserved13These instructions are not implemented but are reserved for future use. Do not use these instructions.13TAP Controller State Diagram14TAP Controller Block Diagram15TAP Electrical Characteristics15TAP AC Switching Characteristics16TAP Timing and Test Conditions16Identification Register Definitions17Scan Register Sizes17Instruction Codes17Boundary Scan Order18Power Up Sequence in DDR-II+ SRAM19Power Up Sequence19DLL Constraints19Power Up Waveforms19Maximum Ratings20Operating Range20Electrical Characteristics20DC Electrical Characteristics20AC Electrical Characteristics21Capacitance21Thermal Resistance21AC Test Loads and Waveforms22Switching Characteristics23Switching Waveforms24Read/Write/Deselect Sequence [29, 30, 31, 32]24Ordering Information25Package Diagram27Document History Page28Taille: 720 koPages: 28Language: EnglishOuvrir le manuel