Manuels d'utilisation pour HP Intel Xeon W3680

Table des matières

• 1 Introduction

  9
  • 1.1 Terminology

    9
    • 1.1.1 Processor Terminology

      10
  • 1.2 References

    11
• 2 Electrical Specifications

  13
  • 2.1 Power and Ground Lands

    13
  • 2.2 Decoupling Guidelines

    13
    • 2.2.1 VCC Decoupling

      13
    • 2.2.2 Vtt Decoupling

      13
    • 2.2.3 FSB Decoupling

      14
  • 2.3 Voltage Identification

    14
  • 2.4 Market Segment Identification (MSID)

    16
  • 2.5 Reserved, Unused, and TESTHI Signals

    16
  • 2.6 Voltage and Current Specification

    17
    • 2.6.1 Absolute Maximum and Minimum Ratings

      17
    • 2.6.2 DC Voltage and Current Specification

      18
    • 2.6.3 VCC Overshoot

      22
    • 2.6.4 Die Voltage Validation

      22
  • 2.7 Signaling Specifications

    23
    • 2.7.1 FSB Signal Groups

      23
    • 2.7.2 CMOS and Open Drain Signals

      25
    • 2.7.3 Processor DC Specifications

      25
    • 2.7.4 Clock Specifications

      27
    • 2.7.5 Front Side Bus Clock (BCLK[1:0]) and Processor Clocking

      27
    • 2.7.6 FSB Frequency Select Signals (BSEL[2:0])

      28
    • 2.7.7 Phase Lock Loop (PLL) and Filter

      28
    • 2.7.8 BCLK[1:0] Specifications (CK505 based Platforms)

      29
    • 2.7.9 BCLK[1:0] Specifications (CK410 based Platforms)

      30
  • 2.8 PECI DC Specifications

    31
• 3 Package Mechanical Specifications

  33
  • 3.1 Package Mechanical Drawing

    34
    • 3.1.1 Processor Component Keep-Out Zones

      38
    • 3.1.2 Package Loading Specifications

      38
    • 3.1.3 Package Handling Guidelines

      38
    • 3.1.4 Package Insertion Specifications

      38
    • 3.1.5 Processor Mass Specification

      39
    • 3.1.6 Processor Materials

      39
  • 3.2 Processor Markings

    39
    • 3.2.1 Processor Land Coordinates

      41
• 4 Land Listing and Signal Descriptions

  43
  • 4.1 Processor Land Assignments

    43
  • 4.2 Alphabetical Signals Reference

    66
• 5 Thermal Specifications and Design Considerations

  73
  • 5.1 Processor Thermal Specifications

    73
    • 5.1.1 Thermal Specifications

      73
    • 5.1.2 Thermal Metrology

      78
  • 5.2 Processor Thermal Features

    78
    • 5.2.1 Thermal Monitor

      78
    • 5.2.2 Thermal Monitor 2

      79
    • 5.2.3 On-Demand Mode

      80
    • 5.2.4 PROCHOT# Signal

      81
    • 5.2.5 THERMTRIP# Signal

      81
  • 5.3 Thermal Diode

    81
  • 5.4 Platform Environment Control Interface (PECI)

    83
    • 5.4.1 Introduction

      83
    • 5.4.2 PECI Specifications

      86
• 6 Features

  87
  • 6.1 Power-On Configuration Options

    87
  • 6.2 Clock Control and Low Power States

    87
    • 6.2.1 Normal State

      88
    • 6.2.2 HALT and Extended HALT Powerdown States

      88
    • 6.2.3 Stop Grant and Extended Stop Grant States

      89
    • 6.2.4 Extended HALT Snoop State, HALT Snoop State, Extended Stop Grant Snoop State, and Stop Grant Snoop State

      90
  • 6.3 Enhanced Intel® SpeedStep® Technology

    91
• 7 Boxed Processor Specifications

  93
  • 7.1 Mechanical Specifications

    94
    • 7.1.1 Boxed Processor Cooling Solution Dimensions

      94
    • 7.1.2 Boxed Processor Fan Heatsink Weight

      95
    • 7.1.3 Boxed Processor Retention Mechanism and Heatsink Attach Clip Assembly

      95
  • 7.2 Electrical Requirements

    95
    • 7.2.1 Fan Heatsink Power Supply

      95
  • 7.3 Thermal Specifications

    97
    • 7.3.1 Boxed Processor Cooling Requirements

      97
    • 7.3.2 Variable Speed Fan

      99
• 8 Debug Tools Specifications

  101
  • 8.1 Logic Analyzer Interface (LAI)

    101
    • 8.1.1 Mechanical Considerations

      101
    • 8.1.2 Electrical Considerations

      101