Manuels d'utilisation pour Intel 2 Duo T9500

Table des matières

• Contents

  3
• 1 Introduction

  7
  • 1.1 Terminology

    8
  • 1.2 References

    9
• 2 Low Power Features

  11
  • 2.1 Clock Control and Low-Power States

    11
    • 2.1.1 Core Low-Power State Descriptions

      13
      • 2.1.1.1 Core C0 State

        13
      • 2.1.1.2 Core C1/AutoHALT Power-Down State

        13
      • 2.1.1.3 Core C1/MWAIT Power-Down State

        14
      • 2.1.1.4 Core C2 State

        14
      • 2.1.1.5 Core C3 State

        14
      • 2.1.1.6 Core C4 State

        14
      • 2.1.1.7 Core C6 State

        15
    • 2.1.2 Package Low-Power State Descriptions

      15
      • 2.1.2.1 Normal State

        15
      • 2.1.2.2 Stop-Grant State

        15
      • 2.1.2.3 Stop-Grant Snoop State

        16
      • 2.1.2.4 Sleep State

        16
      • 2.1.2.5 Deep Sleep State

        16
      • 2.1.2.6 Deeper Sleep State

        17
  • 2.2 Enhanced Intel SpeedStep® Technology

    19
  • 2.3 Extended Low-Power States

    20
  • 2.4 FSB Low-Power Enhancements

    21
    • 2.4.1 Dynamic FSB Frequency Switching

      21
    • 2.4.2 Intel® Dynamic Acceleration Technology

      22
  • 2.5 VID-x

    22
  • 2.6 Processor Power Status Indicator (PSI-2) Signal

    22
• 3 Electrical Specifications

  23
  • 3.1 Power and Ground Pins

    23
  • 3.2 FSB Clock (BCLK[1:0]) and Processor Clocking

    23
  • 3.3 Voltage Identification

    23
  • 3.4 Catastrophic Thermal Protection

    26
  • 3.5 Reserved and Unused Pins

    27
  • 3.6 FSB Frequency Select Signals (BSEL[2:0])

    27
  • 3.7 FSB Signal Groups

    27
  • 3.8 CMOS Signals

    29
  • 3.9 Maximum Ratings

    29
  • 3.10 Processor DC Specifications

    30
• 5 Thermal Specifications

  71
  • 5.1 Thermal Features

    73
    • 5.1.1 Thermal Diode

      73
    • 5.1.2 Intel® Thermal Monitor

      74
    • 5.1.3 Digital Thermal Sensor

      76
  • 5.2 Out of Specification Detection

    77
  • 5.3 PROCHOT# Signal Pin

    77