Manuels d'utilisation pour Intel 366 MHz

Table des matières

• Title Page

  1
• Contents

  3
• Revision History

  9
• 1.0 Introduction

  11
  • 1.1 Terminology

    11
    • 1.1.1 Package Terminology

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    • 1.1.2 Processor Naming Convention

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      • Table 1. Processor Identification

        13
  • 1.2 References

    14
• 2.0 Electrical Specifications

  15
  • 2.1 System Bus and Vref

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  • 2.2 Clock Control and Low Power States

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    • 2.2.1 Normal State—State 1

      16
    • 2.2.2 AutoHALT Power Down State—State 2

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      • Figure 1. Clock Control State Machine

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    • 2.2.3 Stop-Grant State—State 3

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    • 2.2.4 HALT/Grant Snoop State—State 4

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    • 2.2.5 Sleep State—State 5

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    • 2.2.6 Deep Sleep State—State 6

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    • 2.2.7 Clock Control

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  • 2.3 Power and Ground Pins

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    • 2.3.1 Phase Lock Loop (PLL) Power

      19
  • 2.4 Processor Decoupling

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    • 2.4.1 System Bus AGTL+ Decoupling

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  • 2.5 Voltage Identification

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    • Table 2. Voltage Identification Definition

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  • 2.6 System Bus Unused Pins

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  • 2.7 Processor System Bus Signal Groups

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    • Table 3. Intel® Celeron® Processor System Bus Signal Groups

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    • 2.7.1 Asynchronous Vs. Synchronous for System Bus Signals

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    • 2.7.2 System Bus Frequency Select Signal (BSEL[1:0])

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  • 2.8 Test Access Port (TAP) Connection

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  • 2.9 Maximum Ratings

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    • Table 4. Absolute Maximum Ratings

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  • 2.10 Processor DC Specifications

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    • Table 5. Voltage and Current Specifications (Sheet 1 of 5)

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    • Table 6. AGTL+ Signal Groups DC Specifications

      31
    • Table 7. Non-AGTL+ Signal Group DC Specifications

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  • 2.11 AGTL+ System Bus Specifications

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    • Table 8. Processor AGTL+ Bus Specifications

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  • 2.12 System Bus AC Specifications

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    • Table 9. System Bus AC Specifications (Clock) at the Processor Edge Fingers (for S.E.P. Package)

      35
    • Table 10. System Bus AC Specifications (Clock) at the Processor Core Pins (for Both S.E.P. and PG...

      36
    • Table 11. System Bus AC Specifications (SET Clock)1, 2

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    • Table 12. Valid Intel® Celeron® Processor System Bus, Core Frequency 

      38
    • Table 13. System Bus AC Specifications (AGTL+ Signal Group) at the Processor Edge Fingers (for S....

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    • Table 14. System Bus AC Specifications (AGTL+ Signal Group) at the Processor Core Pins (for S.E.P...

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    • Table 15. Processor System Bus AC Specifications (AGTL+ Signal Group) at the Processor Core Pins ...

      40
    • Table 16. System Bus AC Specifications (AGTL+ Signal Group) at the Processor Core Pins (for FC-PG...

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    • Table 17. System Bus AC Specifications (CMOS Signal Group) at the Processor Edge Fingers (for S.E...

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    • Table 18. System Bus AC Specifications (CMOS Signal Group) at the Processor Core Pins (for Both S...

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    • Table 19. System Bus AC Specifications (CMOS Signal Group) 1, 2, 3, 4

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    • Table 20. System Bus AC Specifications (Reset Conditions) (for Both S.E.P. and PPGA Packages)

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    • Table 21. System Bus AC Specifications (Reset Conditions) (for the FC-PGA/FC-PGA2 Packages)

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    • Table 22. System Bus AC Specifications (APIC Clock and APIC I/O) at the Processor Edge Fingers (f...

      43
    • Table 23. System Bus AC Specifications (APIC Clock and APIC I/O) at the Processor Core Pins (For ...

      44
    • Table 24. System Bus AC Specifications (APIC Clock and APIC I/O)1, 2, 3

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    • Table 25. System Bus AC Specifications (TAP Connection) at the Processor Edge Fingers (For S.E.P....

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    • Table 26. System Bus AC Specifications (TAP Connection) at the Processor Core Pins (for Both S.E....

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    • Table 27. System Bus AC Specifications (TAP Connection)1, 2, 3

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    • Figure 2. BCLK to Core Logic Offset

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    • Figure 3. BCLK*, PICCLK, and TCK Generic Clock Waveform

      49
    • Figure 4. System Bus Valid Delay Timings

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    • Figure 5. System Bus Setup and Hold Timings

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    • Figure 6. System Bus Reset and Configuration Timings (For the S.E.P. and PPGA Packages)

      50
    • Figure 7. System Bus Reset and Configuration Timings (For the FC-PGA/FC-PGA2 Package)

      50
    • Figure 8. Power-On Reset and Configuration Timings

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    • Figure 9. Test Timings (TAP Connection)

      51
    • Figure 10. Test Reset Timings

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• 3.0 System Bus Signal Simulations

  52
  • 3.1 System Bus Clock (BCLK) Signal Quality Specifications and Measurement Guidelines

    52
    • Table 28. BCLK Signal Quality Specifications for Simulation at the Processor Core (for Both S.E.P...

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    • Table 29. BCLK/PICCLK Signal Quality Specifications for Simulation at the Processor Pins (for the...

      53
    • Figure 11. BCLK, TCK, PICCLK Generic Clock Waveform at the Processor Core Pins

      53
    • Table 30. BCLK Signal Quality Guidelines for Edge Finger Measurement (for the S.E.P. Package)

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    • Figure 12. BCLK, TCK, PICCLK Generic Clock Waveform at the Processor Edge Fingers

      54
  • 3.2 AGTL+ Signal Quality Specifications and Measurement Guidelines

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    • Table 31. AGTL+ Signal Groups Ringback Tolerance Specifications at the Processor Core (For Both t...

      55
    • Table 32. AGTL+ Signal Groups Ringback Tolerance Specifications at the Processor Pins (For FC-PGA...

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    • Table 33. AGTL+ Signal Groups Ringback Tolerance Guidelines for Edge Finger Measurement on the S....

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    • Figure 13. Low to High AGTL+ Receiver Ringback Tolerance

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  • 3.3 Non-AGTL+ Signal Quality Specifications and Measurement Guidelines

    57
    • Figure 14. Non-AGTL+ Overshoot/Undershoot, Settling Limit, and Ringback

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    • 3.3.1 Overshoot/Undershoot Guidelines

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    • 3.3.2 Ringback Specification

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      • Table 34. Signal Ringback Specifications for Non-AGTL+ Signal Simulation at the Processor Core (S...

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      • Table 35. Signal Ringback Guidelines for Non-AGTL+ Signal Edge Finger Measurement (S.E.P. Package)

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      • Table 36. Signal Ringback Specifications for Non-AGTL+ Signal Simulation at the Processor Pins (F...

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    • 3.3.3 Settling Limit Guideline

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  • 3.4 AGTL+ Signal Quality Specifications and Measurement Guidelines (FC-PGA/FC-PGA2 Packages)

    59
    • 3.4.1 Overshoot/Undershoot Guidelines (FC-PGA/FC-PGA2 Packages)

      59
    • 3.4.2 Overshoot/Undershoot Magnitude (FC-PGA/FC-PGA2 Packages)

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    • 3.4.3 Overshoot/Undershoot Pulse Duration (FC-PGA/FC-PGA2 Packages)

      60
    • 3.4.4 Activity Factor (FC-PGA/FC-PGA2 Packages)

      60
    • 3.4.5 Reading Overshoot/Undershoot Specification Tables (FC-PGA/ FC-PGA2 Packages)

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      • Table 37. Example Platform Information

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    • 3.4.6 Determining if a System meets the Overshoot/Undershoot Specifications (FC-PGA/FC-PGA2 Packa...

      62
      • Table 38. 66MHz AGTL+ Signal Group Overshoot/Undershoot Tolerance at Processor Pins (FC-PGA/FC-P...

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      • Table 39. 33MHz CMOS Signal Group Overshoot/Undershoot Tolerance at Processor Pins (FC-PGA/FC-PG...

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      • Figure 15. Maximum Acceptable AGTL+ Overshoot/Undershoot Waveform (FC-PGA/FC-PGA2 Packages)

        63
  • 3.5 Non-AGTL+ Signal Quality Specifications and Measurement Guidelines

    64
    • Figure 16. Non-AGTL+ Overshoot/Undershoot, Settling Limit, and Ringback 1

      64
• 4.0 Thermal Specifications and Design Considerations

  65
  • 4.1 Thermal Specifications

    65
    • Table 40. Processor Power for the PPGA and FC-PGA Packages

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    • Table 41. Intel® Celeron® Processor for the FC-PGA2 Package Thermal Design Power 1

      67
    • Figure 17. Processor Functional Die Layout (CPUID 0686h)(1)

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    • Figure 18. Processor Functional Die Layout (up to CPUID 0683h)

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    • 4.1.1 Thermal Diode

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      • Table 42. Thermal Diode Parameters (S.E.P. and PPGA Packages)

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      • Table 43. Thermal Diode Parameters (FC-PGA/FC-PGA2 Packages)

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      • Table 44. Thermal Diode Interface

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• 5.0 Mechanical Specifications

  69
  • 5.1 S.E.P. Package

    69
    • 5.1.1 Materials Information

      69
      • Figure 19. Processor Substrate Dimensions (S.E.P. Package)

        70
      • Figure 20. Processor Substrate Primary/Secondary Side Dimensions (S.E.P. Package)

        70
    • 5.1.2 Signal Listing (S.E.P. Package)

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      • Table 45. S.E.P. Package Signal Listing by Pin Number

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      • Table 46. S.E.P. Package Signal Listing by Signal Name

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  • 5.2 PPGA Package

    79
    • 5.2.1 PPGA Package Materials Information

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      • Figure 21. Package Dimensions (PPGA Package)

        79
      • Table 47. Package Dimensions (PPGA Package)

        80
      • Table 48. Information Summary (PPGA Package)

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    • 5.2.2 PPGA Package Signal Listing

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      • Figure 22. PPGA Package (Pin Side View)

        81
      • Table 49. PPGA Package Signal Listing by Pin Number

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      • Table 50. PPGA Package Signal Listing in Order by Signal Name

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  • 5.3 FC-PGA/FC-PGA2 Packages

    92
    • 5.3.1 FC-PGA Mechanical Specifications

      92
      • Figure 23. Package Dimensions (FC-PGA Package)

        92
      • Table 51. Package Dimensions (FC-PGA Package)

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      • Table 52. Processor Die Loading Parameters (FC-PGA Package)

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    • 5.3.2 Mechanical Specifications (FC-PGA2 Package)

      94
      • Figure 24. Package Dimensions (FC-PGA2 Package)

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      • Table 53. Package Dimensions (FC-PGA2 Package)

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      • Table 54. Processor Case Loading Parameters (FC-PGA2 Package)

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      • Figure 25. Volumetric Keep-Out

        96
      • Figure 26. Component Keep-Out

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    • 5.3.3 FC-PGA/FC-PGA2 Package Signal List

      97
      • Figure 27. Package Dimensions (FC-PGA/FC-PGA2 Packages)

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      • Table 55. FC-PGA/FC-PGA2 Signal Listing in Order by Signal Name

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      • Table 56. FC-PGA/FC-PGA2 Signal Listing in Order by Pin Number

        103
  • 5.4 Processor Markings (PPGA/FC-PGA/FC-PGA2 Packages)

    108
    • Figure 28. Top Side Processor Markings (PPGA Package)

      108
    • Figure 29. Top Side Processor Markings (FC-PGA Package)

      108
    • Figure 30. Top Side Processor Markings (FC-PGA2 Package)

      108
  • 5.5 Heatsink Volumetric Keepout Zone Guidelines

    109
• 6.0 Boxed Processor Specifications

  110
  • 6.1 Mechanical Specifications for the Boxed Intel® Celeron® Processor

    110
    • 6.1.1 Mechanical Specifications for the S.E.P. Package

      110
      • Figure 31. Retention Mechanism for the Boxed Intel® Celeron® Processor in the S.E.P. Package

        111
      • Figure 32. Side View Space Requirements for the Boxed Processor in the S.E.P. Package

        111
      • Figure 33. Front View Space Requirements for the Boxed Processor in the S.E.P. Package

        112
      • Table 57. Boxed Processor Fan Heatsink Spatial Dimensions for the S.E.P. Package

        112
    • 6.1.2 Mechanical Specifications for the PPGA Package

      113
      • Figure 34. Boxed Intel® Celeron® Processor in the PPGA Package

        113
      • Figure 35. Side View Space Requirements for the Boxed Processor in the PPGA Package

        113
    • 6.1.3 Mechanical Specifications for the FC-PGA/FC-PGA2 Packages

      114
      • Figure 36. Conceptual Drawing of the Boxed Intel® Celeron® Processor in the 370-Pin Socket (FC-PG...

        114
      • Figure 37. Dimensions of Mechanical Step Feature in Heatsink Base for the FC-PGA/ FC-PGA2 Packages

        114
  • 6.2 Thermal Specifications

    115
    • 6.2.1 Thermal Requirements for the Boxed Intel® Celeron® Processor

      115
      • Figure 38. Top View Airspace Requirements for the Boxed Processor in the S.E.P. Package

        115
      • Figure 39. Side View Airspace Requirements for the Boxed Intel® Celeron® Processor in the FC-PGA/...

        116
      • Figure 40. Volumetric Keepout Requirements for The Boxed Fan Heatsink

        116
      • Figure 41. Clip Keepout Requirements for the 370-Pin (Top View)

        117
  • 6.3 Electrical Requirements for the Boxed Intel® Celeron® Processor

    117
    • 6.3.1 Electrical Requirements

      117
      • Figure 42. Boxed Processor Fan Heatsink Power Cable Connector Description

        118
      • Table 58. Fan Heatsink Power and Signal Specifications

        118
      • Figure 43. Motherboard Power Header Placement for the S.E.P. Package

        119
      • Figure 44. Motherboard Power Header Placement Relative to the 370-pin Socket

        119
• 7.0 Processor Signal Description

  120
  • Table 59. Alphabetical Signal Reference (Sheet 1 of 7)

    120
  • 7.1 Signal Summaries

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    • Table 60. Output Signals

      126
    • Table 61. Input Signals

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    • Table 62. Input/Output Signals (Single Driver)

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    • Table 63. Input/Output Signals (Multiple Driver)

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