Manuels d'utilisation pour Intel 80287

Table des matières

• Advanced Features

  1
• Memory Management

  1
• Task Management

  1
• Protection Mechanisms

  1
• Support for Operating Systems

  1
• Memory Organization and Segmentation

  2
• Registers

  2
• General Registers

  2
• Index, Pointer, and Base Registers

  2
• Status and Control Registers

  2
• Addressing Modes

  2
• Memory Addressing Modes

  2
• Offset Computation

  2
• Memory Mode

  2
• Input/Output

  2
• Memory-Mapped I/O

  2
• Interrupts and Exceptions

  2
• Hierarchy of Instruction Sets

  2
• Data Movement Instructions

  3
• General-Purpose Data Movement Instructions

  3
• Stack Manipulation Instructions

  3
• Flag Operation with the Basic Instruction Set

  3
• Status Flags

  3
• Control Flags

  3
• Arithmetic Instructions

  3
• Addition Instructions

  3
• Subtraction Instructions

  3
• Multiplication Instructions

  3
• Division Instructions

  3
• Logical Instructions

  3
• Boolean Operation Instructions

  3
• Shift and Rotate Instructions

  3
• Shift Instructions

  3
• Rotate Instructions

  3
• Type Conversion and No-Operation Instructions

  3
• Test and Compare Instructions

  3
• Control Transfer Instructions

  3
• Unconditional Transfer Instructions

  3
• Jump Instruction

  3
• Call Instruction

  3
• Return and Return from Interrupt Instruction

  3
• Conditional Transfer Instructions

  3
• Loop Instructions

  3
• Software-Generated Interrupts

  3
• Software Interrupt Instruction

  3
• Character Translation and String Instructions

  3
• Translate Instruction

  3
• String Manipulation Instructions and Repeat Prefixes

  3
• Address Manipulation Instructions

  3
• Flag Control Instructions

  3
• Carry Flag Control Instructions

  3
• Direction Flag Control Instructions

  3
• Flag Transfer Instructions

  3
• Packed BCD Adjustment Instructions

  3
• Unpacked BCD Adjustment Instructions

  3
• Trusted and Privileged Restrictions on POPF and IRET

  3
• Machine State Instructions

  3
• Input and Output Instructions

  3
• Processor Extension Instructions

  3
• Processor Extension Synchronization Instructions

  3
• Numeric Data Processor Instructions

  3
• Arithmetic Instructions

  3
• Comparison Instructions

  3
• Transcendental Instructions

  3
• Data Transfer Instructions

  3
• Constant Instructions

  3
• Block I/O Instructions

  4
• High-Level Instructions

  4
• Addressing and Segmentation

  5
• Interrupt Handling

  5
• Interrupt Vector Table

  5
• Interrupt Priorities

  5
• Interrupt Procedures

  5
• Reserved and Dedicated Interrupt Vectors

  5
• System Initialization

  5
• Memory Management Overview

  6
• Descriptor Tables

  6
• Segments and Segment Descriptors

  6
• Segment Address Translation Registers

  6
• Introduction

  7
• Types of Protection

  7
• Protection Implementation

  7
• Memory Management and Protection

  7
• Separation of Address Spaces

  7
• LDT and GDT Access Checks

  7
• Type Validation

  7
• Privilege Levels and Protection

  7
• Example of Using Four Privilege Levels

  7
• Privilege Usage

  7
• Segment Descriptor

  7
• Data Accesses

  7
• Code Segment Access

  7
• Data Access Restriction by Privilege Level

  7
• POinter Privilege Stamping via ARPL

  7
• Gates

  7
• Call Gates

  7
• Intra-Level Transfers via Call Gate

  7
• Inter-Level Control Transfer via Call Gates

  7
• Inter-Level Returns

  7
• Introduction

  8
• Task State Segments and Descriptors

  8
• Task State Segment Descriptors

  8
• Task Switching

  8
• Task Linking

  8
• Task Gates

  8
• Interrupt Descriptor Table

  9
• Hardware Initiated Interrupts

  9
• Software Initiated Interrupts

  9
• Interrupt Gates and Trap Gates

  9
• Task Gates and Interrupt Tasks

  9
• Protection Exceptions and Reserved Vectors

  9
• Invalid OP-Code (Interrupt 6)

  9
• Double Fault (Interrupt 8)

  9
• Processor Extension Segment Overrun (Interrupt 9)

  9
• Invalid Task State Segment (Interrupt 10)

  9
• Not Present (Interrupt 11)

  9
• Stack Fault (Interrupt 12)

  9
• General Protection Fault (Interrupt 13)

  9
• Additional Exceptions and Interrupts

  9
• Single Step Interrupt (Interrupt 1)

  9
• Descriptor Table Registers

  10
• System Control Instructions

  10
• Machine Status Word

  10
• Privileged and Trusted Instructions

  10
• Initialization

  10
• Real Address Mode

  10
• Protected Mode

  10
• Conforming Code Segments

  11
• Pointer Validation

  11
• Pointer Integrity: RPL and the "Trojan Horse Problem"

  11
• NPX Context Switching

  11
• Bytes and Words in Memory

  2
• 80286 Base Architecture Register Set

  2
• Real Address Mode Segment Selector Interpretation

  2
• Protected Mode Segment Selector Interpretation

  2
• 80286 Stack

  2
• Stack Operation

  2
• BP Usage as a Stack Frame Base Pointer

  2
• Flags Register

  2
• Two-Component Address

  2
• Complex Addressing Modes

  2
• Memory-Mapped I/O

  2
• Hierarchy of Instructions

  2
• POP

  3
• POPA

  3
• SAL and SHL

  3
• SHR

  3
• SAR

  3
• ROL

  3
• ROR

  3
• RCL

  3
• RCR

  3
• LAHF and SAHF

  3
• PUSHF and POPF

  3
• Formal Definition of the ENTER Instruction

  4
• Variable Access in Nested Procedures

  4
• Stack Frame for MAIN at Level 1

  4
• Stack Frame for Procedure C at Level 3 Called from B

  4
• Interrupt Vector Table for Real Address Mode

  5
• Format of the Segment Selector Component

  6
• Address Spaces and Task Isolation

  6
• Special Purpose Descriptors or System Segment Descriptors (S=O)

  6
• LDT Descriptor

  6
• Segment Descriptor Access Bytes

  6
• Memory Management Registers

  6
• Descriptor Loading

  6
• Addressing Segments of a Module within a Task

  7
• Local and Global Descriptor Table Definitions

  7
• Error Code Format (on the stack)

  7
• Selector Fields

  7
• Access Byte Examples

  7
• Pointer Privilege Stamping

  7
• Gate Descriptor Format

  7
• Call Gate

  7
• Stack Contents after an Inter-Level Call

  7
• Task State Segment and TSS Registers

  8
• Task Gate Descriptor

  8
• Task Switch Through a Task Gate

  8
• Interrupt Descriptor Table Definition

  9
• IDT Selector Error Code

  9
• Trap/Interrupt Gate Descriptors

  9
• Local and Global Descriptor Table Definition

  10
• Interrupt Descriptor Table Definition

  10
• Data Type for Global Descriptor Table and Interrupt Descriptor Table

  10
• Dynamic Segment Relocation and Expansion of Segment Limit

  11
• Example of NPX Context Switching

  11
• Implied Segment Usage by Index, Pointer, and Base Registers

  2
• Memory Operand Addressing Modes

  2
• 80286 Interrupt Vector Assignments (Real Address Mode)

  2
• Status Flags' Functions

  3
• Control Flags' Functions

  3
• Interpretation of Conditional Transfers

  3
• Interrupt Processing Order

  5
• Dedicated and Reserved Interrupt Vectors in Real Address Mode

  5
• Call Gate Checks

  7
• Inter-Level Return Checks

  7
• Checks Made during a Task Switch

  8
• Effect of a Task Switch on BUSY and NT Bits and the Link Word

  8
• Trap and Interrupt Gate Checks

  9
• Interrupt and Gate Interactions

  9
• Reserved Exceptions and Interrupts

  9
• Conditions That Invalidate the TSS

  9
• MSW 8it Functions

  10
• Recommended MSW Encodings for Processor Extension Control

  10
• NPXContextSwitching

  11
• ModRM Values

  8
• Hexadecimal Values for the Access Rights 8yte

  8
• + 10000H

  1
• Introduction to the 80287 Numeric Processor Extension

  1
• Ease of Use

  1
• Applications

  1
• Upgradability

  1
• Hardware Interface

  1
• 80287 Numeric Processor Architecture

  1
• The NPX Status Word

  1
• Control Word

  1
• The NPXTag Word

  1
• The NPX Instruction and Data Pointers

  1
• Computation Fundamentals

  1
• Number System

  1
• Data Types and Formats

  1
• Binary Integers

  1
• Real Numbers

  1
• Rounding Control

  1
• Precision Control

  1
• Infinity Control

  1
• Special Computational Situations

  1
• Nonnormal Real Numbers

  1
• Denormals and Gradual Underflow

  1
• Un normals-Descendents of Denormal Operands

  1
• Infinity

  1
• NaN (Not a Number)

  1
• Indefinite

  1
• Numeric Exceptions

  1
• Invalid Operation

  1
• Zero Divisor

  1
• Denormalized Operand

  1
• Numeric Overflow and Underflow

  1
• Inexact Result

  1
• Software Exception Handling

  1
• Compatibility with the 8087 NPX

  2
• Numeric Operands

  2
• Arithmetic Instructions

  2
• Comparison Instructions

  2
• Constant Instructions

  2
• Instruction Set Reference Information

  2
• Instruction Execution Time

  2
• Instruction Length

  2
• Programming Facilities

  2
• High-Level Languages

  2
• ASM286

  2
• Defining Data

  2
• Addressing Modes

  2
• COlTlparative Programming Example

  2
• Instruction Synchronization

  2
• Data Synchronization

  2
• Error Synchronization

  2
• , Incorrect Error Synchronization

  2
• Real-Address Mode and Protected Virtual-Address Mode

  3
• Processor Initialization and Control

  3
• System Initialization

  3
• Recognizing the 80287 NPX

  3
• Initializing the 80287

  3
• Handling Numeric Processing Exceptions

  3
• Exception Recovery· Examples

  3
• Conditional Bra,nching Examples

  4
• Exception Handling Examples

  4
• Floating-point to ASCII Conversion Examples

  4
• Function Partitioning

  4
• Special Instructions

  4
• Scalin"g the Value

  4
• Inaccur~cy in Scaling

  4
• Avoiding Underflow and Overflow

  4
• FPTAN and FPREM

  4
• Cosine Uses Sine Code

  4
• Evolution and Performance of Numeric Processors

  1
• '80287 NPX Block Diagram

  1
• 80287 Tag Word Format

  1
• 80287 Instruction and Data Pointer Image in Memory

  1
• FSAVE/FRSTOR Memory Layout

  2
• Sample 80287 Constants

  2
• Status Word RECORD Definition

  2
• Sample PL/M-286 Program

  2
• Sample ASM286 Program

  2
• Instructions and Register Stack

  2
• Nonconcurrent FIST Instruction Code Macro

  2
• Error Synchronization Examples

  2
• Software Routine to Recognize the 80287

  3
• Conditional Branching for Compares

  4
• Conditional Branching for FXAM

  4
• Full-State Exception Handler

  4
• Reduced-Latency Exception Handler

  4
• Reentrant Exception Handler

  4
• Floating-Point to ASCII Conversion Routine

  4
• Calculating Trigonometric Functions

  4
• Numeric Processing Speed Comparisons

  1
• Numeric Data Types

  1
• Principal NPX Instructions

  1
• Interpreting the NPX Condition Codes

  1
• Real Number Notation

  1
• Rounding Modes

  1
• Denormalization Process

  1
• Unnormal Operands and Results

  1
• Zero Operands and Results

  1
• Masked Overflow Response with Directed Rounding

  1
• Infinity Operands and Results

  1
• Packed Decimal Encodings

  1
• Real and Long Real Encodings

  1
• Temporary Real Encodings

  1
• Exception Conditions and Masked Responses

  1
• Data Transfer Instructions

  2
• Arithmetic Instructions

  2
• Basic Arithmetic Instructions and Operands

  2
• Comparison Instructions

  2
• Condition Code Interpretation after FCOM

  2
• Condition Code Interpretation after FTST

  2
• Transcendental Instructions

  2
• Constant Instructions

  2
• Key to Operand Types

  2
• Execuiiur I PE:naitiE:5

  2
• Instruction Set Reference Data

  2
• PLfM-286 Built-In Procedures

  2
• Addressing Mode Examples

  2
• NPX Processor State Following Initialization

  3
• Precedence of NPX Exceptions

  3
• Thh lub1'DUUnW will c.leul.t. the v.lue of 10

  4
• PENNSYLVANIA i

  59714
• tt~/

  23040