Manuels d'utilisation pour Intel Celeron D 345

Table des matières

• Contents

  3
• Figures

  5
• Tables

  6
• Revision History

  7
• Intel® Celeron® D Processor 300 Sequence Features

  8
• Intel® Celeron® D Processor 300D Sequence

  1
• 1 Introduction

  9
  • 1.1 Terminology

    9
    • 1.1.1 Processor Packaging Terminology

      10
  • 1.2 References

    11
• 2 Electrical Specifications

  13
  • 2.1 Power and Ground Lands

    13
  • 2.2 Decoupling Guidelines

    13
    • 2.2.1 VCC Decoupling

      13
    • 2.2.2 VTT Decoupling

      14
    • 2.2.3 FSB Decoupling

      14
  • 2.3 Voltage Identification

    14
  • 2.4 Reserved, Unused, and TESTHI Signals

    16
  • 2.5 Voltage and Current Specification

    17
    • 2.5.1 Absolute Maximum and Minimum Ratings

      17
    • 2.5.2 DC Voltage and Current Specification

      18
    • 2.5.3 VCC Overshoot

      21
    • 2.5.4 Die Voltage Validation

      22
  • 2.6 Signaling Specifications

    22
    • 2.6.1 FSB Signal Groups

      23
    • 2.6.2 GTL+ Asynchronous Signals

      25
    • 2.6.3 Processor DC Specifications

      25
      • 2.6.3.1 GTL+ Front Side Bus Specifications

        28
  • 2.7 Clock Specifications

    29
    • 2.7.1 Front Side Bus Clock (BCLK[1:0]) and Processor Clocking

      29
    • 2.7.2 FSB Frequency Select Signals (BSEL[2:0])

      30
    • 2.7.3 Phase Lock Loop (PLL) and Filter

      30
    • 2.7.4 BCLK[1:0] Specifications

      32
• 3 Package Mechanical Specifications

  33
  • 3.1 Package Mechanical Drawing

    33
  • 3.2 Processor Component Keep-Out Zones

    37
  • 3.3 Package Loading Specifications

    37
  • 3.4 Package Handling Guidelines

    37
  • 3.5 Package Insertion Specifications

    38
  • 3.6 Processor Mass Specification

    38
  • 3.7 Processor Materials

    38
  • 3.8 Processor Markings

    38
  • 3.9 Processor Land Coordinates

    39
• 4 Land Listing and Signal Descriptions

  41
  • 4.1 Processor Land Assignments

    41
  • 4.2 Alphabetical Signals Reference

    64
• 5 Thermal Specifications and Design Considerations

  75
  • 5.1 Processor Thermal Specifications

    75
    • 5.1.1 Thermal Specifications

      75
    • 5.1.2 Thermal Metrology

      79
  • 5.2 Processor Thermal Features

    79
    • 5.2.1 Thermal Monitor

      79
    • 5.2.2 On-Demand Mode

      80
    • 5.2.3 PROCHOT# Signal

      81
    • 5.2.4 THERMTRIP# Signal

      81
    • 5.2.5 TCONTROL and Fan Speed Reduction

      81
    • 5.2.6 Thermal Diode

      81
• 6 Features

  85
  • 6.1 Power-On Configuration Options

    85
  • 6.2 Clock Control and Low Power States

    85
    • 6.2.1 Normal State

      86
    • 6.2.2 HALT and Enhanced HALT Powerdown States

      86
      • 6.2.2.1 HALT Powerdown State

        87
      • 6.2.2.2 Enhanced HALT Powerdown State

        87
    • 6.2.3 Stop Grant State

      87
    • 6.2.4 Enhanced HALT Snoop or HALT Snoop State, Stop Grant Snoop State

      88
      • 6.2.4.1 HALT Snoop State, Stop Grant Snoop State

        88
      • 6.2.4.2 Enhanced HALT Snoop State

        88
• 7 Boxed Processor Specifications

  89
  • 7.1 Mechanical Specifications

    89
    • 7.1.1 Boxed Processor Cooling Solution Dimensions

      89
    • 7.1.2 Boxed Processor Fan Heatsink Weight

      91
    • 7.1.3 Boxed Processor Retention Mechanism and Heatsink Attach Clip Assembly

      91
  • 7.2 Electrical Requirements

    91
    • 7.2.1 Fan Heatsink Power Supply

      91
  • 7.3 Thermal Specifications

    93
    • 7.3.1 Boxed Processor Cooling Requirements

      93
• 8 Debug Tools Specifications

  95
  • 8.1 Logic Analyzer Interface (LAI)

    95
    • 8.1.1 Mechanical Considerations

      95
    • 8.1.2 Electrical Considerations

      95