Manuel D’Utilisation (AW8063801115901)Table des matières1 Introduction111.1 Processor Feature Details131.1.1 Supported Technologies131.2 Interfaces131.2.1 System Memory Support131.2.2 PCI Express*141.2.3 Direct Media Interface (DMI)151.2.4 Platform Environment Control Interface (PECI)161.2.5 Processor Graphics161.2.6 Embedded DisplayPort* (eDP*)171.2.7 Intel® Flexible Display Interface (Intel® FDI)171.3 Power Management Support171.3.1 Processor Core171.3.2 System171.3.3 Memory Controller171.3.4 PCI Express*171.3.5 Direct Media Interface (DMI)171.3.6 Processor Graphics Controller (GT)181.3.7 Thermal Management Support181.4 Processor Family SKU Definition181.5 Package191.6 Processor Compatibility191.7 Terminology201.8 Related Documents232 Interfaces252.1 System Memory Interface252.1.1 System Memory Technology Supported252.1.2 System Memory Timing Support262.1.3 System Memory Organization Modes272.1.3.1 Single-Channel Mode272.1.3.2 Dual-Channel Mode – Intel® Flex Memory Technology Mode272.1.4 Rules for Populating Memory Slots282.1.5 Technology Enhancements of Intel® Fast Memory Access (Intel® FMA)292.1.5.1 Just-in-Time Command Scheduling292.1.5.2 Command Overlap292.1.5.3 Out-of-Order Scheduling292.1.6 Data Scrambling292.1.7 DRAM Clock Generation292.1.8 DDR3 Reference Voltage Generation302.2 PCI Express* Interface302.2.1 PCI Express* Architecture302.2.1.1 Transaction Layer312.2.1.2 Data Link Layer312.2.1.3 Physical Layer312.2.2 PCI Express* Configuration Mechanism322.2.3 PCI Express* Graphics332.2.3.1 PCI Express* Lanes Connection332.3 Direct Media Interface (DMI)342.3.1 DMI Error Flow342.3.2 Processor / PCH Compatibility Assumptions342.3.3 DMI Link Down342.4 Processor Graphics Controller (GT)352.4.1 3D and Video Engines for Graphics Processing352.4.1.1 3D Engine Execution Units352.4.1.2 3D Pipeline362.4.1.3 Video Engine362.4.1.4 2D Engine372.4.2 Processor Graphics Display382.4.2.1 Display Planes382.4.2.2 Display Pipes392.4.2.3 Display Ports392.4.2.4 Embedded DisplayPort* (eDP*)392.4.3 Intel® Flexible Display Interface (Intel® FDI)392.4.4 Multi Graphics Controllers Multi-Monitor Support402.5 Platform Environment Control Interface (PECI)402.6 Interface Clocking402.6.1 Internal Clocking Requirements403 Technologies413.1 Intel® Virtualization Technology (Intel® VT)413.1.1 Intel® Virtualization Technology (Intel® VT) for IA-32, Intel® 64 and Intel® Architecture (Intel® VT-x) Objectives413.1.2 Intel® Virtualization Technology (Intel® VT) for IA-32, Intel® 64 and Intel® Architecture (Intel® VT-x) Features423.1.3 Intel® Virtualization Technology (Intel® VT) for Directed I/O (Intel® VT-d) Objectives423.1.4 Intel® Virtualization Technology (Intel® VT) for Directed I/O (Intel® VT-d) Features433.1.5 Intel® Virtualization Technology (Intel® VT) for Directed I/O (Intel® VT-d) Features Not Supported433.2 Intel® Trusted Execution Technology (Intel® TXT)443.3 Intel® Hyper-Threading Technology (Intel® HT Technology)443.4 Intel® Turbo Boost Technology453.4.1 Intel®Turbo Boost Technology Frequency453.4.2 Intel® Turbo Boost Technology Graphics Frequency463.5 Intel® Advanced Vector Extensions (Intel® AVX)463.6 Security and Cryptography Technologies473.6.1 Intel® Advanced Encryption Standard New Instructions (Intel® AES-NI)473.6.2 PCLMULQDQ Instruction473.6.3 RDRAND Instruction473.7 Intel® 64 Architecture x2APIC483.8 Supervisor Mode Execution Protection (SMEP)493.9 Power Aware Interrupt Routing (PAIR)494 Power Management514.1 Advanced Configuration and Power Interface (ACPI) States Supported524.1.1 System States524.1.2 Processor Core / Package Idle States524.1.3 Integrated Memory Controller States524.1.4 PCI Express* Link States534.1.5 Direct Media Interface (DMI) States534.1.6 Processor Graphics Controller States534.1.7 Interface State Combinations534.2 Processor Core Power Management544.2.1 Enhanced Intel® SpeedStep® Technology544.2.2 Low-Power Idle States554.2.3 Requesting Low-Power Idle States564.2.4 Core C-states574.2.4.1 Core C0 State574.2.4.2 Core C1 / C1E State574.2.4.3 Core C3 State574.2.4.4 Core C6 State574.2.4.5 Core C7 State584.2.4.6 C-State Auto-Demotion584.2.5 Package C-States584.2.5.1 Package C0604.2.5.2 Package C1/C1E604.2.5.3 Package C3 State604.2.5.4 Package C6 State604.2.5.5 Package C7 State614.2.5.6 Dynamic L3 Cache Sizing614.3 Integrated Memory Controller (IMC) Power Management614.3.1 Disabling Unused System Memory Outputs614.3.2 DRAM Power Management and Initialization624.3.2.1 Initialization Role of CKE634.3.2.2 Conditional Self-Refresh634.3.2.3 Dynamic Power Down Operation644.3.2.4 DRAM I/O Power Management644.3.3 DDR Electrical Power Gating (EPG)644.4 PCI Express* Power Management654.5 DMI Power Management654.6 Graphics Power Management654.6.1 Intel® Rapid Memory Power Management (Intel® RMPM) (also known as CxSR)654.6.2 Intel® Graphics Performance Modulation Technology (Intel® GPMT)654.6.3 Graphics Render C-State664.6.4 Intel® Smart 2D Display Technology (Intel® S2DDT)664.6.5 Intel® Graphics Dynamic Frequency664.6.6 Display Power Savings Technology 6.0 (DPST)674.6.7 Automatic Display Brightness (ADB)674.6.8 Intel® Seamless Display Refresh Rate Switching Technology (Intel® SDRRS Technology)674.7 Graphics Thermal Power Management685 Thermal Management695.1 Thermal Considerations695.2 Intel® Turbo Boost Technology Power Monitoring705.3 Intel® Turbo Boost Technology Power Control705.3.1 Package Power Control705.3.2 Power Plane Control725.3.3 Turbo Time Parameter725.4 Configurable Thermal Design Power (cTDP) and Low Power Mode (LPM)725.4.1 Configurable TDP (cTDP)725.4.2 Low Power Mode735.5 Thermal and Power Specifications745.6 Thermal Management Features775.6.1 Adaptive Thermal Monitor775.6.1.1 TCC Activation Offset785.6.1.2 Frequency / Voltage Control785.6.1.3 Clock Modulation805.6.2 Digital Thermal Sensor805.6.2.1 Digital Thermal Sensor Accuracy (Taccuracy)815.6.2.2 Fan Speed Control with Digital Thermal Sensor815.6.3 PROCHOT# Signal815.6.3.1 Bi-Directional PROCHOT#815.6.3.2 Voltage Regulator Protection versus PROCHOT#825.6.3.3 Thermal Solution Design and PROCHOT# Behavior825.6.3.4 Low-Power States and PROCHOT# Behavior825.6.3.5 THERMTRIP# Signal835.6.3.6 Critical Temperature Detection835.6.4 On-Demand Mode835.6.4.1 MSR Based On-Demand Mode835.6.4.2 I/O Emulation-Based On-Demand Mode835.6.5 Memory Thermal Management845.6.6 Platform Environment Control Interface (PECI)846 Signal Description856.1 System Memory Interface Signals866.2 Memory Reference and Compensation Signals886.3 Reset and Miscellaneous Signals886.4 PCI Express*-based Interface Signals896.5 Embedded DisplayPort* (eDP*) Signals896.6 Intel® Flexible Display (Intel® FDI) Interface Signals896.7 Direct Media Interface (DMI) Signals906.8 Phase Lock Loop (PLL) Signals906.9 Test Access Points (TAP) Signals906.10 Error and Thermal Protection Signals916.11 Power Sequencing Signals926.12 Processor Power Signals936.13 Sense Signals936.14 Ground and Non-Critical to Function (NCTF) Signals946.15 Processor Internal Pull-Up / Pull-Down Resistors947 Electrical Specifications957.1 Power and Ground Pins957.2 Decoupling Guidelines957.2.1 Voltage Rail Decoupling957.2.2 PLL Power Supply957.3 Voltage Identification (VID)967.4 System Agent (SA) Vcc VID997.5 Reserved or Unused Signals997.6 Signal Groups1007.7 Test Access Port (TAP) Connection1027.8 Component Storage Condition Specifications (Prior to Board Attach)1027.9 DC Specifications1037.9.1 Voltage and Current Specifications1037.10 Platform Environmental Control Interface (PECI) DC Specifications1107.10.1 PECI Bus Architecture1107.10.2 PECI DC Characteristics1117.10.3 Input Device Hysteresis1118 Processor Pin, Signal, and Package Information1138.1 Processor Pin Assignments1138.2 Package Mechanical Information1609 DDR Data Swizzling169Taille: 3 MoPages: 172Language: EnglishOuvrir le manuel
Manuel D’Utilisation (AV8063801116102)Table des matièresDesktop 3rd Generation Intel® Core™ Processor Family, Desktop Intel® Pentium® Processor Family, and Desktop Intel® Celeron® Processor Family1Revision History81 Introduction91.1 Processor Feature Details111.1.1 Supported Technologies111.2 Interfaces111.2.1 System Memory Support111.2.2 PCI Express*121.2.3 Direct Media Interface (DMI)141.2.4 Platform Environment Control Interface (PECI)141.2.5 Processor Graphics141.2.6 Intel® Flexible Display Interface (Intel® FDI)151.3 Power Management Support151.3.1 Processor Core151.3.2 System151.3.3 Memory Controller151.3.4 PCI Express*151.3.5 Direct Media Interface (DMI)161.3.6 Processor Graphics Controller (GT)161.3.7 Thermal Management Support161.4 Processor SKU Definitions161.5 Package171.6 Processor Compatibility181.7 Terminology191.8 Related Documents222 Interfaces232.1 System Memory Interface232.1.1 System Memory Technology Supported232.1.2 System Memory Timing Support242.1.3 System Memory Organization Modes252.1.3.1 Single-Channel Mode252.1.3.2 Dual-Channel Mode – Intel® Flex Memory Technology Mode252.1.4 Rules for Populating Memory Slots262.1.5 Technology Enhancements of Intel® Fast Memory Access (Intel® FMA)272.1.5.1 Just-in-Time Command Scheduling272.1.5.2 Command Overlap272.1.5.3 Out-of-Order Scheduling272.1.6 Data Scrambling272.1.7 DDR3 Reference Voltage Generation272.2 PCI Express* Interface282.2.1 PCI Express* Architecture282.2.1.1 Transaction Layer292.2.1.2 Data Link Layer292.2.1.3 Physical Layer292.2.2 PCI Express* Configuration Mechanism302.2.3 PCI Express* Port312.2.3.1 PCI Express* Lanes Connection312.3 Direct Media Interface (DMI)322.3.1 DMI Error Flow322.3.2 Processor / PCH Compatibility Assumptions322.3.3 DMI Link Down322.4 Processor Graphics Controller (GT)332.4.1 3D and Video Engines for Graphics Processing332.4.1.1 3D Engine Execution Units332.4.1.2 3D Pipeline342.4.1.3 Video Engine342.4.1.4 2D Engine352.4.2 Processor Graphics Display362.4.2.1 Display Planes362.4.2.2 Display Pipes372.4.2.3 Display Ports372.4.3 Intel® Flexible Display Interface (Intel® FDI)372.4.4 Multi Graphics Controllers Multi-Monitor Support372.5 Platform Environment Control Interface (PECI)382.6 Interface Clocking382.6.1 Internal Clocking Requirements383 Technologies393.1 Intel® Virtualization Technology (Intel® VT)393.1.1 Intel® Virtualization Technology (Intel® VT) for IA-32, Intel® 64 and Intel® Architecture (Intel® VT-x) Objectives393.1.2 Intel® Virtualization Technology (Intel® VT) for IA-32, Intel® 64 and Intel® Architecture (Intel® VT-x) Features403.1.3 Intel® Virtualization Technology (Intel® VT) for Directed I/O (Intel® VT-d) Objectives403.1.4 Intel® Virtualization Technology (Intel® VT) for Directed I/O (Intel® VT-d) Features413.1.5 Intel® Virtualization Technology (Intel® VT) for Directed I/O (Intel® VT-d) Features Not Supported413.2 Intel® Trusted Execution Technology (Intel® TXT)423.3 Intel® Hyper-Threading Technology (Intel® HT Technology)423.4 Intel® Turbo Boost Technology433.4.1 Intel® Turbo Boost Technology Frequency433.4.2 Intel® Turbo Boost Technology Graphics Frequency433.5 Intel® Advanced Vector Extensions (Intel® AVX)443.6 Security and Cryptography Technologies443.6.1 Intel® Advanced Encryption Standard New Instructions (Intel® AES-NI)443.6.2 PCLMULQDQ Instruction443.6.3 RDRAND Instruction453.7 Intel® 64 Architecture x2APIC453.8 Supervisor Mode Execution Protection (SMEP)463.9 Power Aware Interrupt Routing (PAIR)464 Power Management474.1 Advanced Configuration and Power Interface (ACPI) States Supported484.1.1 System States484.1.2 Processor Core / Package Idle States484.1.3 Integrated Memory Controller States484.1.4 PCI Express* Link States494.1.5 Direct Media Interface (DMI) States494.1.6 Processor Graphics Controller States494.1.7 Interface State Combinations494.2 Processor Core Power Management504.2.1 Enhanced Intel® SpeedStep® Technology504.2.2 Low-Power Idle States504.2.3 Requesting Low-Power Idle States524.2.4 Core C-states524.2.4.1 Core C0 State524.2.4.2 Core C1 / C1E State534.2.4.3 Core C3 State534.2.4.4 Core C6 State534.2.4.5 C-State Auto-Demotion534.2.5 Package C-States544.2.5.1 Package C0554.2.5.2 Package C1/C1E554.2.5.3 Package C3 State564.2.5.4 Package C6 State564.3 Integrated Memory Controller (IMC) Power Management564.3.1 Disabling Unused System Memory Outputs564.3.2 DRAM Power Management and Initialization574.3.2.1 Initialization Role of CKE584.3.2.2 Conditional Self-Refresh584.3.2.3 Dynamic Power Down Operation594.3.2.4 DRAM I/O Power Management594.3.3 DDR Electrical Power Gating (EPG)594.4 PCI Express* Power Management604.5 DMI Power Management604.6 Graphics Power Management604.6.1 Intel® Rapid Memory Power Management (Intel® RMPM) (also known as CxSR)604.6.2 Intel® Graphics Performance Modulation Technology (Intel® GPMT)604.6.3 Graphics Render C-State604.6.4 Intel® Smart 2D Display Technology (Intel® S2DDT)614.6.5 Intel® Graphics Dynamic Frequency614.7 Graphics Thermal Power Management615 Thermal Management636 Signal Description656.1 System Memory Interface Signals666.2 Memory Reference and Compensation Signals676.3 Reset and Miscellaneous Signals686.4 PCI Express*-based Interface Signals696.5 Intel® Flexible Display (Intel® FDI) Interface Signals696.6 Direct Media Interface (DMI) Signals706.7 Phase Lock Loop (PLL) Signals706.8 Test Access Points (TAP) Signals706.9 Error and Thermal Protection Signals716.10 Power Sequencing Signals726.11 Processor Power Signals736.12 Sense Signals736.13 Ground and Non-Critical to Function (NCTF) Signals746.14 Processor Internal Pull-Up / Pull-Down Resistors747 Electrical Specifications757.1 Power and Ground Lands757.2 Decoupling Guidelines757.2.1 Voltage Rail Decoupling757.3 Processor Clocking (BCLK[0], BCLK#[0])767.3.1 Phase Lock Loop (PLL) Power Supply767.4 VCC Voltage Identification (VID)767.5 System Agent (SA) VCC VID807.6 Reserved or Unused Signals807.7 Signal Groups807.8 Test Access Port (TAP) Connection827.9 Storage Conditions Specifications837.10 DC Specifications847.10.1 Voltage and Current Specifications847.11 Platform Environmental Control Interface (PECI) DC Specifications907.11.1 PECI Bus Architecture907.11.2 DC Characteristics917.11.3 Input Device Hysteresis918 Processor Land and Signal Information938.1 Processor Land Assignments939 DDR Data Swizzling109Taille: 770 koPages: 112Language: EnglishOuvrir le manuel
