Manuels d'utilisation pour Intel i5-4210Y

Table des matières

• Contents

  3
  • Figures

    6
  • Tables

    7
• Revision History

  9
• 1.0 Introduction

  10
  • 1.1 Supported Technologies

    11
  • 1.2 Power Management Support

    12
  • 1.3 Thermal Management Support

    12
  • 1.4 Package Support

    13
  • 1.5 Processor Testability

    13
  • 1.6 Terminology

    13
  • 1.7 Related Documents

    16
• 2.0 Interfaces

  17
  • 2.1 System Memory Interface

    17
    • 2.1.1  System Memory Technology Supported

      17
    • 2.1.2 System Memory Timing Support

      19
    • 2.1.3 System Memory Organization Modes

      19
    • 2.1.4 System Memory Frequency

      20
    • 2.1.5  Intel® Fast Memory Access (Intel® FMA) Technology Enhancements

      20
    • 2.1.6  Data Scrambling

      21
    • 2.1.7 DRAM Clock Generation

      21
    • 2.1.8 DRAM Reference Voltage Generation

      21
  • 2.2 Processor Graphics

    22
  • 2.3 Processor Graphics Controller (GT)

    22
    • 2.3.1 3D and Video Engines for Graphics Processing

      22
  • 2.4 Digital Display Interface (DDI)

    24
  • 2.5 Platform Environmental Control Interface (PECI)

    29
    • 2.5.1 PECI Bus Architecture

      29
• 3.0 Technologies

  31
  • 3.1 Intel® Virtualization Technology (Intel® VT)

    31
  • 3.2 Intel® Trusted Execution Technology (Intel® TXT)

    35
  • 3.3 Intel® Hyper-Threading Technology (Intel® HT Technology)

    36
  • 3.4 Intel® Turbo Boost Technology 2.0

    37
  • 3.5 Intel® Advanced Vector Extensions 2.0 (Intel® AVX2)

    37
  • 3.6 Intel® Advanced Encryption Standard New Instructions (Intel® AES-NI)

    38
  • 3.7 Intel® 64 Architecture x2APIC

    38
  • 3.8  Power Aware Interrupt Routing (PAIR)

    40
  • 3.9 Execute Disable Bit

    40
  • 3.10 Intel® Boot Guard

    40
  • 3.11  Supervisor Mode Execution Protection (SMEP)

    40
  • 3.12  Intel® Transactional Synchronization Extensions - New Instructions (Intel® TSX-NI)

    41
• 4.0 Power Management

  42
  • 4.1 Advanced Configuration and Power Interface (ACPI) States Supported

    43
  • 4.2 Processor Core Power Management

    44
    • 4.2.1 Enhanced Intel® SpeedStep® Technology Key Features

      44
    • 4.2.2 Low-Power Idle States

      45
    • 4.2.3 Requesting Low-Power Idle States

      46
    • 4.2.4 Core C-State Rules

      46
    • 4.2.5 Package C-States

      48
    • 4.2.6 Package C-States and Display Resolutions

      51
  • 4.3 Integrated Memory Controller (IMC) Power Management

    53
    • 4.3.1 Disabling Unused System Memory Outputs

      53
    • 4.3.2 DRAM Power Management and Initialization

      53
      • 4.3.2.1 Initialization Role of CKE

        55
      • 4.3.2.2 Conditional Self-Refresh

        55
      • 4.3.2.3 Dynamic Power-Down

        55
      • 4.3.2.4 DRAM I/O Power Management

        56
    • 4.3.3 DDR Electrical Power Gating (EPG)

      56
  • 4.4 Graphics Power Management

    56
    • 4.4.1 Intel® Rapid Memory Power Management (Intel® RMPM)

      56
    • 4.4.2 Graphics Render C-State

      56
    • 4.4.3 Intel® Smart 2D Display Technology (Intel® S2DDT)

      57
    • 4.4.4 Intel® Graphics Dynamic Frequency

      57
    • 4.4.5  Intel® Display Power Saving Technology (Intel® DPST)

      57
    • 4.4.6 Intel® Automatic Display Brightness

      58
    • 4.4.7 Intel® Seamless Display Refresh Rate Technology (Intel® SDRRS Technology)

      58
• 5.0 Thermal Management

  59
  • 5.1 Thermal Considerations

    59
  • 5.2 Intel® Turbo Boost Technology 2.0 Power Monitoring

    60
  • 5.3 Intel® Turbo Boost Technology 2.0 Power Control

    60
    • 5.3.1 Package Power Control

      60
    • 5.3.2 Turbo Time Parameter

      61
  • 5.4 Configurable TDP (cTDP) and Low-Power Mode

    61
    • 5.4.1 Configurable TDP

      61
    • 5.4.2 Low-Power Mode

      62
  • 5.5 Thermal and Power Specifications

    62
  • 5.6 Thermal Management Features

    65
    • 5.6.1 Adaptive Thermal Monitor

      65
      • 5.6.1.1 Thermal Control Circuit (TCC) Activation Offset

        66
      • 5.6.1.2 Frequency / Voltage Control

        66
      • 5.6.1.3 Clock Modulation

        67
    • 5.6.2 Digital Thermal Sensor

      67
      • 5.6.2.1 Digital Thermal Sensor Accuracy (Taccuracy)

        68
      • 5.6.2.2  Fan Speed Control with Digital Thermal Sensor

        68
    • 5.6.3 PROCHOT# Signal

      68
      • 5.6.3.1 Bi-Directional PROCHOT#

        68
      • 5.6.3.2 Voltage Regulator Protection using PROCHOT#

        69
      • 5.6.3.3 Thermal Solution Design and PROCHOT# Behavior

        69
      • 5.6.3.4 Low-Power States and PROCHOT# Behavior

        69
      • 5.6.3.5 THERMTRIP# Signal

        69
      • 5.6.3.6 Critical Temperature Detection

        69
    • 5.6.4 On-Demand Mode

      70
      • 5.6.4.1 MSR Based On-Demand Mode

        70
      • 5.6.4.2 I/O Emulation-Based On-Demand Mode

        70
    • 5.6.5 Intel® Memory Thermal Management

      70
    • 5.6.6 Scenario Design Power (SDP)

      71
• 6.0 Signal Description

  72
  • 6.1 System Memory Interface Signals

    72
  • 6.2 Memory Compensation and Miscellaneous Signals

    75
  • 6.3 Reset and Miscellaneous Signals

    76
  • 6.4 embedded DisplayPort* (eDP*) Signals

    77
  • 6.5 Display Interface Signals

    77
  • 6.6 Testability Signals

    77
  • 6.7 Error and Thermal Protection Signals

    78
  • 6.8 Power Sequencing Signals

    79
  • 6.9 Processor Power Signals

    79
  • 6.10 Sense Signals

    80
  • 6.11 Ground and Non-Critical to Function (NCTF) Signals

    80
  • 6.12 Processor Internal Pull-Up / Pull-Down Terminations

    80
• 7.0 Electrical Specifications

  82
  • 7.1 Integrated Voltage Regulator

    82
  • 7.2 Power and Ground Pins

    82
  • 7.3 VCC Voltage Identification (VID)

    82
  • 7.4 Reserved or Unused Signals

    87
  • 7.5 Signal Groups

    87
  • 7.6 Test Access Port (TAP) Connection

    89
  • 7.7  DC Specifications

    89
  • 7.8 Voltage and Current Specifications

    90
    • 7.8.1 Platform Environment Control Interface (PECI) DC Characteristics

      96
    • 7.8.2 Input Device Hysteresis

      97
• 8.0 Package Specifications

  98
  • 8.1 Package Mechanical Attributes

    98
  • 8.2 Package Loading Specifications

    98
  • 8.3 Package Storage Specifications

    99
• 9.0 Processor Ball and Signal Information

  100