Manuels d'utilisation pour Intel MFS5520VI

Table des matières

• 1. Introduction

  7
  • 1.1 Chapter Outline

    7
  • 1.2 Intel® Compute Module Use Disclaimer

    7
• 2. Product Overview

  8
  • 2.1 Intel® Compute Module MFS5520VI Feature Set

    8
  • 2.2 Compute Module Layout

    9
    • 2.2.1 Connector and Component Locations

      9
    • 2.2.2 External I/O Connector Locations

      9
    • 2.2.3 Compute Module Mechanical Drawings

      11
• 3. Functional Architecture

  12
  • 3.1 Intel® Xeon® processor

    13
    • 3.1.1 Processor Support

      13
      • 3.1.1.1 Processor Population Rules

        13
    • 3.1.2 Mixed Processor Configuration

      13
    • 3.1.3 Turbo Mode

      15
    • 3.1.4 Hyper-Threading

      15
    • 3.1.5 Intel® QuickPath Interconnect

      15
    • 3.1.6 Unified Retention System Support

      16
  • 3.2 Memory Subsystem

    17
    • 3.2.1 Intel® QuickPath Memory Controller

      17
      • 3.2.1.1 Intel® Compute Module MFS5520VI Supported Memory

        17
    • 3.2.2 Publishing Compute Module Memory

      17
    • 3.2.3 Memory Map and Population Rules

      18
      • 3.2.3.1 Memory Subsystem Nomenclature

        18
    • 3.2.4 Memory RAS

      19
      • 3.2.4.1 RAS Features

        19
      • 3.2.4.2 Channel Independent Mode

        19
      • 3.2.4.3 Channel Mirroring Mode

        19
        • 3.2.4.3.1 Minimum DDR3 DIMM Population for Channel Mirroring

          20
        • 3.2.4.3.2 Mirroring DIMM Population Rules Variance across Nodes

          20
    • 3.2.5 Memory Upgrade Rules

      21
  • 3.3 Intel® 5520 Chipset IOH

    23
  • 3.4 Intel® 82801JR I/O Controller Hub (ICH10R)

    23
    • 3.4.1 PCI Subsystem

      24
    • 3.4.2 USB 2.0 Support

      24
  • 3.5 Integrated Baseboard Management Controller

    25
    • 3.5.1 Floppy Disk Controller

      27
    • 3.5.2 Keyboard and Mouse Support

      27
    • 3.5.3 Wake-up Control

      27
  • 3.6 Video Support

    27
    • 3.6.1 Video Modes

      27
  • 3.7 Network Interface Controller (NIC)

    27
    • 3.7.1 Direct Cache Access (DCA)

      28
  • 3.8 Intel® Virtualization Technology for Directed I/O (Intel® VT-d)

    28
• 4. Connector/Header Locations and Pin-outs

  28
  • 4.1 Board Connector Information

    29
  • 4.2 Power Connectors

    29
  • 4.3 I/O Connector Pin-out Definition

    30
    • 4.3.1 VGA Connector

      30
    • 4.3.2 I/O Mezzanine Card Connector

      30
    • 4.3.3 Midplane Signal Connector

      34
    • 4.3.4 Serial Port Connector

      35
    • 4.3.5 USB 2.0 Connectors

      35
• 5. Jumper Block Settings

  36
  • 5.1 Recovery Jumper Blocks

    37
    • 5.1.1 CMOS Clear and Password Clear Usage Procedure

      38
    • 5.1.2 Integrated BMC Force Update Procedure

      38
    • 5.1.3 Integrated BMC Initialization

      39
• 6. Product Regulatory Requirements

  40
  • 6.1 Product Regulatory Requirements

    40
  • 6.2 Product Regulatory Compliance and Safety Markings

    40
  • 6.3 Product Environmental/Ecology Requirements

    40