Manuels d'utilisation pour Intel Quad-core Intel Xeon DP L5320 Passive

Table des matières

• 1 Introduction

  9
  • 1.1 Terminology

    11
  • 1.2 State of Data

    13
  • 1.3 References

    13
• 2 Electrical Specifications

  15
  • 2.1 Front Side Bus and GTLREF

    15
  • 2.2 Power and Ground Lands

    16
  • 2.3 Decoupling Guidelines

    16
    • 2.3.1 VCC Decoupling

      16
    • 2.3.2 VTT Decoupling

      16
    • 2.3.3 Front Side Bus AGTL+ Decoupling

      17
  • 2.4 Front Side Bus Clock (BCLK[1:0]) and Processor Clocking

    17
    • 2.4.1 Front Side Bus Frequency Select Signals (BSEL[2:0])

      18
    • 2.4.2 PLL Power Supply

      19
  • 2.5 Voltage Identification (VID)

    19
  • 2.6 Reserved, Unused, or Test Signals

    21
  • 2.7 Front Side Bus Signal Groups

    22
  • 2.8 CMOS Asynchronous and Open Drain Asynchronous Signals

    24
  • 2.9 Test Access Port (TAP) Connection

    24
  • 2.10 Platform Environmental Control Interface (PECI) DC Specifications

    24
    • 2.10.1 DC Characteristics

      24
    • 2.10.2 Input Device Hysteresis

      25
  • 2.11 Mixing Processors

    25
  • 2.12 Absolute Maximum and Minimum Ratings

    26
  • 2.13 Processor DC Specifications

    27
    • 2.13.1 Flexible Motherboard Guidelines (FMB)

      27
    • 2.13.2 VCC Overshoot Specification

      40
    • 2.13.3 Die Voltage Validation

      41
  • 2.14 AGTL+ FSB Specifications

    41
• 3 Mechanical Specifications

  45
  • 3.1 Package Mechanical Drawings

    45
  • 3.2 Processor Component Keepout Zones

    49
  • 3.3 Package Loading Specifications

    49
  • 3.4 Package Handling Guidelines

    50
  • 3.5 Package Insertion Specifications

    50
  • 3.6 Processor Mass Specifications

    50
  • 3.7 Processor Materials

    50
  • 3.8 Processor Markings

    51
  • 3.9 Processor Land Coordinates

    51
• 4 Land Listing

  55
  • 4.1 Quad-Core Intel® Xeon® Processor 5300 Series Pin Assignments

    55
    • 4.1.1 Land Listing by Land Name

      55
    • 4.1.2 Land Listing by Land Number

      67
• 5 Signal Definitions

  77
  • 5.1 Signal Definitions

    77
• 6 Thermal Specifications

  85
  • 6.1 Package Thermal Specifications

    85
    • 6.1.1 Thermal Specifications

      85
  • 6.2

    93
    • 6.2.1 Thermal Metrology

      95
  • 6.3 Processor Thermal Features

    96
    • 6.3.1 Thermal Monitor Features

      96
    • 6.3.2 Thermal Monitor (TM1)

      96
    • 6.3.3 Thermal Monitor 2

      97
    • 6.3.4 On-Demand Mode

      98
    • 6.3.5 PROCHOT# Signal

      99
    • 6.3.6 FORCEPR# Signal

      99
    • 6.3.7 THERMTRIP# Signal

      100
  • 6.4 Platform Environment Control Interface (PECI)

    100
    • 6.4.1 Introduction

      100
    • 6.4.2 PECI Specifications

      101
• 7 Features

  103
  • 7.1 Power-On Configuration Options

    103
  • 7.2 Clock Control and Low Power States

    103
    • 7.2.1 Normal State

      104
    • 7.2.2 HALT or Extended HALT State

      104
    • 7.2.3 Stop-Grant State

      106
    • 7.2.4 Extended HALT Snoop or HALT Snoop State, Stop Grant Snoop State

      107
  • 7.3 Enhanced Intel SpeedStep® Technology

    107
• 8 Boxed Processor Specifications

  109
  • 8.1 Introduction

    109
  • 8.2 Mechanical Specifications

    111
    • 8.2.1 Boxed Processor Heat Sink Dimensions (CEK)

      111
    • 8.2.2 Boxed Processor Heat Sink Weight

      119
    • 8.2.3 Boxed Processor Retention Mechanism and Heat Sink Support (CEK)

      119
  • 8.3 Electrical Requirements

    119
    • 8.3.1 Fan Power Supply (Active CEK)

      119
    • 8.3.2 Boxed Processor Cooling Requirements

      120
  • 8.4 Boxed Processor Contents

    121
• 9 Debug Tools Specifications

  123
  • 9.1 Debug Port System Requirements

    123
  • 9.2 Target System Implementation

    123
    • 9.2.1 System Implementation

      123
  • 9.3 Logic Analyzer Interface (LAI)

    123
    • 9.3.1 Mechanical Considerations

      124
    • 9.3.2 Electrical Considerations

      124