Manuels d'utilisation pour Intel Xeon X5450

Table des matières

• Quad-Core Intel® Xeon® Processor 5400 Series

  1
• 1 Introduction

  9
  • 1.1 Terminology

    10
  • 1.2 State of Data

    13
  • 1.3 References

    13
• 2 Quad-Core Intel® Xeon® Processor 5400 Series Electrical Specifications

  15
  • 2.1 Front Side Bus and GTLREF

    15
  • 2.2 Power and Ground Lands

    16
  • 2.3 Decoupling Guidelines

    16
    • 2.3.1 VCC Decoupling

      16
    • 2.3.2 VTT Decoupling

      16
    • 2.3.3 Front Side Bus AGTL+ Decoupling

      16
  • 2.4 Front Side Bus Clock (BCLK[1:0]) and Processor Clocking

    17
    • 2.4.1 Front Side Bus Frequency Select Signals (BSEL[2:0])

      17
    • 2.4.2 PLL Power Supply

      18
  • 2.5 Voltage Identification (VID)

    18
  • 2.6 Reserved, Unused, and Test Signals

    21
  • 2.7 Front Side Bus Signal Groups

    22
  • 2.8 CMOS Asynchronous and Open Drain Asynchronous Signals

    24
  • 2.9 Test Access Port (TAP) Connection

    24
  • 2.10 Platform Environmental Control Interface (PECI) DC Specifications

    24
    • 2.10.1 DC Characteristics

      24
    • 2.10.2 Input Device Hysteresis

      25
  • 2.11 Mixing Processors

    26
  • 2.12 Absolute Maximum and Minimum Ratings

    26
  • 2.13 Processor DC Specifications

    27
    • 2.13.1 Flexible Motherboard Guidelines (FMB)

      27
    • 2.13.2 VCC Overshoot Specification

      38
    • 2.13.3 Die Voltage Validation

      39
  • 2.14 AGTL+ FSB Specifications

    39
• 3 Mechanical Specifications

  43
  • 3.1 Package Mechanical Drawings

    43
  • 3.2 Processor Component Keepout Zones

    47
  • 3.3 Package Loading Specifications

    47
  • 3.4 Package Handling Guidelines

    48
  • 3.5 Package Insertion Specifications

    48
  • 3.6 Processor Mass Specifications

    48
  • 3.7 Processor Materials

    48
  • 3.8 Processor Markings

    48
  • 3.9 Processor Land Coordinates

    49
• 4 Land Listing

  51
  • 4.1 Quad-Core Intel® Xeon® Processor 5400 Series Pin Assignments

    51
    • 4.1.1 Land Listing by Land Name

      51
    • 4.1.2 Land Listing by Land Number

      61
• 5 Signal Definitions

  71
  • 5.1 Signal Definitions

    71
• 6 Thermal Specifications

  79
  • 6.1 Package Thermal Specifications

    79
    • 6.1.1 Thermal Specifications

      79
    • 6.1.2 Thermal Metrology

      90
  • 6.2 Processor Thermal Features

    90
    • 6.2.1 Intel® Thermal Monitor Features

      90
    • 6.2.2 On-Demand Mode

      92
    • 6.2.3 PROCHOT# Signal

      93
    • 6.2.4 FORCEPR# Signal

      93
    • 6.2.5 THERMTRIP# Signal

      94
  • 6.3 Platform Environment Control Interface (PECI)

    94
    • 6.3.1 Introduction

      94
    • 6.3.2 PECI Specifications

      96
• 7 Features

  97
  • 7.1 Power-On Configuration Options

    97
  • 7.2 Clock Control and Low Power States

    97
    • 7.2.1 Normal State

      98
    • 7.2.2 HALT or Extended HALT State

      98
    • 7.2.3 Stop-Grant State

      100
    • 7.2.4 Extended HALT Snoop or HALT Snoop State, Stop Grant Snoop State

      101
  • 7.3 Enhanced Intel SpeedStep® Technology

    101
• 8 Boxed Processor Specifications

  103
  • 8.1 Introduction

    103
  • 8.2 Mechanical Specifications

    105
    • 8.2.1 Boxed Processor Heat Sink Dimensions (CEK)

      105
    • 8.2.2 Boxed Processor Heat Sink Weight

      113
    • 8.2.3 Boxed Processor Retention Mechanism and Heat Sink Support (CEK)

      113
  • 8.3 Electrical Requirements

    113
    • 8.3.1 Fan Power Supply (Active CEK)

      113
    • 8.3.2 Boxed Processor Cooling Requirements

      114
  • 8.4 Boxed Processor Contents

    115
• 9 Debug Tools Specifications

  117
  • 9.1 Debug Port System Requirements

    117
  • 9.2 Target System Implementation

    117
    • 9.2.1 System Implementation

      117
  • 9.3 Logic Analyzer Interface (LAI)

    117
    • 9.3.1 Mechanical Considerations

      118
    • 9.3.2 Electrical Considerations

      118