Manuel D’UtilisationTable des matièresTABLE OF CONTENTS2LIST OF FIGURES6LIST OF TABLES81 DESCRIPTION92 FEATURE HIGHLIGHTS112.1 General112.2 Microprocessor Interface112.3 HDLC Ethernet Mapping112.4 X.86 (Link Access Protocol for SONET/SDH) Ethernet Mapping112.5 Additional HDLC Controllers in the Integrated T1/E1/J1 Transceiver122.6 Committed Information Rate (CIR) Controller122.7 SDRAM Interface122.8 MAC Interface122.9 T1/E1/J1 Line Interface132.10 Clock Synthesizer132.11 Jitter Attenuator132.12 T1/E1/J1 Framer142.13 TDM Bus142.14 Test and Diagnostics152.15 Specifications Compliance163 APPLICATIONS174 ACRONYMS AND GLOSSARY185 MAJOR OPERATING MODES196 BLOCK DIAGRAMS207 PIN DESCRIPTIONS257.1 Pin Functional Description258 FUNCTIONAL DESCRIPTION418.1 Processor Interface428.1.1 Read-Write/Data Strobe Modes428.1.2 Clear on Read428.1.3 Interrupt and Pin Modes429 ETHERNET MAPPER439.1 Ethernet Mapper Clocks439.1.1 Ethernet Interface Clock Modes459.1.2 Serial Interface Clock Modes459.2 Resets and Low Power Modes469.3 Initialization and Configuration479.4 Global Resources479.5 Per-Port Resources479.6 Device Interrupts489.7 Interrupt Information Registers509.8 Status Registers509.9 Information Registers509.10 Serial Interface509.11 Connections and Queues519.12 Arbiter529.13 Flow Control539.13.1 Full Duplex Flow Control549.13.2 Half Duplex Flow Control559.13.3 Host-Managed Flow Control559.14 Ethernet Interface Port569.14.1 DTE and DCE Mode589.15 Ethernet MAC599.15.1 MII Mode Options61p.15.2 RMII Mode619.15.3 PHY MII Management Block and MDIO Interface629.16 BERT in the Ethernet Mapper629.16.1 Receive Data Interface639.16.1.1 Receive Pattern Detection639.16.1.2 PRBS Synchronization639.16.2 Repetitive Pattern Synchronization649.16.3 Pattern Monitoring649.16.4 Pattern Generation649.16.4.1 Error Insertion659.16.4.2 Performance Monitoring Update659.17 Transmit Packet Processor659.18 Receive Packet Processor669.19 X.86 Encoding and Decoding689.20 Committed Information Rate Controller7110 INTEGRATED T1/E1/J1 TRANSCEIVER7210.1 T1/E1/J1 Clocks7210.2 Per-Channel Operation7310.3 T1/E1/J1 Transceiver Interrupts7310.4 T1 Framer/Formatter Control and Status7410.4.1 T1 Transmit Transparency7410.4.2 AIS-CI and RAI-CI Generation and Detection7410.4.3 T1 Receive-Side Digital-Milliwatt Code Generation7510.5 E1 Framer/Formatter Control and Status7610.5.1 Automatic Alarm Generation7710.6 Per-Channel Loopback7710.7 Error Counters7810.7.1 Line-Code Violation Counter (TR.LCVCR)7810.7.2 Path Code Violation Count Register (TR.PCVCR)7910.7.3 Frames Out-of-Sync Count Register (TR.FOSCR)8010.7.4 E-Bit Counter (TR.EBCR)8010.8 DS0 Monitoring Function8110.9 Signaling Operation8210.9.1 Processor-Based Receive Signaling8210.9.1.1 Change-of-State8210.9.2 Hardware-Based Receive Signaling8310.9.2.1 Receive Signaling Reinsertion at RSERO8310.9.2.2 Force Receive Signaling All Ones8310.9.2.3 Receive Signaling Freeze8310.9.3 Processor-Based Transmit Signaling8410.9.3.1 T1 Mode8410.9.3.2 E1 Mode8510.9.4 Hardware-Based Transmit Signaling8510.10 Per-Channel Idle Code Generation8610.10.1 Idle-Code Programming Examples8710.11 Channel Blocking Registers8810.12 Elastic Stores Operation8810.12.1 Receive Elastic Store8810.12.1.1 T1 Mode8810.12.1.2 E1 Mode8810.12.2 Transmit Elastic Store8910.12.2.1 T1 Mode8910.12.2.2 E1 Mode8910.12.3 Elastic Stores Initialization8910.12.4 Minimum Delay Mode8910.13 G.706 Intermediate CRC-4 Updating (E1 Mode Only)9010.14 T1 Bit-Oriented Code (BOC) Controller9110.14.1 Transmit BOC9110.14.1.1 Transmit a BOC9110.14.2 Receive BOC91Receive a BOC9110.15 Additional (Sa) and International (Si) Bit Operation (E1 Only)9210.15.1 Method 1: Internal Register Scheme Based on Double-Frame9210.15.2 Method 2: Internal Register Scheme Based on CRC4 Multiframe9210.16 Additional HDLC Controllers in T1/E1/J1 Transceiver9310.16.1 HDLC Configuration9310.16.2 FIFO Control9510.16.3 HDLC Mapping9510.16.4 FIFO Information9610.16.5 Receive Packet-Bytes Available9610.16.5.1 Receive HDLC Code Example9610.17 Legacy FDL Support (T1 Mode)9710.17.1 Overview9710.17.2 Receive Section9710.17.3 Transmit Section9810.18 D4/SLC-96 Operation9810.19 Programmable In-Band Loop Code Generation and Detection9910.20 Line Interface Unit (LIU)10010.20.1 LIU Operation10010.20.2 Receiver10010.20.2.1 Receive Level Indicator and Threshold Interrupt10110.20.2.2 Receive G.703 Synchronization Signal (E1 Mode)10110.20.2.3 Monitor Mode10110.20.3 Transmitter10210.20.3.1 Transmit Short-Circuit Detector/Limiter10210.20.3.2 Transmit Open-Circuit Detector10210.20.3.3 Transmit BPV Error Insertion10210.20.3.4 Transmit G.703 Synchronization Signal (E1 Mode)10210.21 MCLK Prescaler10310.22 Jitter Attenuator10310.23 CMI (Code Mark Inversion) Option10310.24 Recommended Circuits10410.25 T1/E1/J1 TRANSCEIVER BERT FUNCTION10810.25.1 BERT Status10810.25.2 BERT Mapping10810.25.3 BERT Repetitive Pattern Set11010.25.4 BERT Bit Counter11010.25.5 BERT Error Counter11010.25.6 BERT Alternating Word-Count Rate11010.26 Payload Error-Insertion Function (T1 Mode Only)11110.26.1 Number-of-Errors Registers11110.27 Programmable Backplane Clock Synthesizer11210.28 Fractional T1/E1 Support11210.29 T1/E1/J1 Transmit Flow Diagrams11311 DEVICE REGISTERS11711.1 Register Bit Maps11811.1.1 Global Ethernet Mapper Register Bit Map11811.1.2 Arbiter Register Bit Map11911.1.3 BERT Register Bit Map11911.1.4 Serial Interface Register Bit Map12011.1.5 Ethernet Interface Register Bit Map12211.1.6 MAC Register Bit Map12311.2 Global Register Definitions for Ethernet Mapper13411.3 Arbiter Registers14311.3.1 Arbiter Register Bit Descriptions14311.4 BERT Registers14411.5 Serial Interface Registers15111.5.1 Serial Interface Transmit and Common Registers15111.5.1.1 Serial Interface Transmit Register Bit Descriptions15111.5.1.2 Transmit HDLC Processor Register Bit Descriptions15211.5.2 X.86 Registers15911.5.3 Receive Serial Interface16111.5.3.1 Receive Serial Register Bit Descriptions16111.6 Ethernet Interface Registers174Ethernet Interface Register Bit Descriptions17411.6.2 MAC Registers18611.7 T1/E1/J1 Transceiver Registers20111.7.1 Number-of-Errors Left Register29912 FUNCTIONAL TIMING30012.1 Functional Serial I/O Timing30012.2 MII and RMII Interfaces30112.3 Transceiver T1 Mode Functional Timing30312.4 E1 Mode30813 OPERATING PARAMETERS31313.1 Thermal Characteristics31413.2 MII Interface31513.3 RMII Interface31713.4 MDIO Interface31913.5 Transmit WAN Interface32013.6 Receive WAN Interface32113.7 SDRAM Timing32213.8 Microprocessor Bus AC Characteristics32413.9 AC Characteristics: Receive-Side32713.10 AC Characteristics: Backplane Clock Timing33113.11 AC Characteristics: Transmit Side33213.12 JTAG Interface Timing33514 JTAG INFORMATION33614.1 JTAG TAP Controller State Machine Description33714.2 Instruction Register33914.3 JTAG ID Codes34114.4 Test Registers34114.4.1 Boundary Scan Register34114.4.2 Bypass Register34114.4.3 Identification Register34114.5 JTAG Functional Timing34215 PACKAGE INFORMATION34315.1 256-Ball BGA (27mm x 27mm) (56-G6004-001)34316 DOCUMENT REVISION HISTORY344Taille: 11 MoPages: 344Language: EnglishOuvrir le manuel