Manuel D’UtilisationTable des matièresDESCRIPTION7FEATURE HIGHLIGHTS8General8Link Aggregation (Inverse Multiplexing)8HDLC8Committed Information Rate (CIR) Controller8X.86 Support8SDRAM Interface9MAC Interface9Microprocessor Interface9Test and Diagnostics9Specifications compliance10APPLICATIONS11ACRONYMS AND GLOSSARY12MAJOR OPERATING MODES13BLOCK DIAGRAMS13PIN DESCRIPTIONS14Pin Functional Description14FUNCTIONAL DESCRIPTION22Processor Interface23Read-Write/Data Strobe Modes23Clear on Read23Interrupt and Pin Modes23Clock Structure23Serial Interface Clock Modes26Ethernet Interface Clock Modes26Resets and Low-Power Modes27Initialization and Configuration28Global Resources28Per-Port Resources28Device Interrupts29Serial Interface31Link Aggregation (IMUX)31Microprocessor Requirements33IMUX Command Protocol34Out of Frame (OOF) Monitoring36Data Transfer36Connections and Queues37Arbiter38Flow Control39Full-Duplex Flow Control40Half-Duplex Flow control41Host-Managed Flow control41Ethernet Interface Port41DTE and DCE Mode43Ethernet MAC46MII Mode47RMII Mode47PHY MII Management Block and MDIO Interface48BERT48BERT Features48Receive Data Interface49Receive Pattern Detection49PRBS Synchronization49Repetitive Pattern Synchronization49Pattern Monitoring50Pattern Generation50Error Insertion50Performance Monitoring Update51Transmit Packet Processor52Receive Packet Processor53X.86 Encoding and Decoding55Committed Information Rate Controller58DEVICE REGISTERS60Register Bit Maps60Global Register Bit Map61Arbiter Register Bit Map62BERT Register Bit Map62Serial Interface Register Bit Map63Ethernet Interface Register Bit Map65MAC Register Bit Map66Global Register Definitions68Arbiter Registers81Arbiter Register Bit Descriptions81BERT Registers82Serial Interface Registers89Serial Interface Transmit and Common Registers89Serial Interface Transmit Register Bit Descriptions89Transmit HDLC Processor Registers90X.86 Registers97Receive Serial Interface99Ethernet Interface Registers112Ethernet Interface Register Bit Descriptions112MAC Registers124FUNCTIONAL TIMING140MII and RMII Interfaces140OPERATING PARAMETERS142Thermal Characteristics143MII Interface144RMII Interface146MDIO Interface148Transmit WAN Interface149Receive WAN Interface150SDRAM Timing151Microprocessor Bus AC Characteristics155JTAG Interface Timing158JTAG INFORMATION159JTAG TAP Controller State Machine Description160Instruction Register162SAMPLE:PRELOAD163BYPASS163EXTEST163CLAMP163HIGHZ163IDCODE163JTAG ID Codes164Test Registers164Boundary Scan Register164Bypass Register164Identification Register164JTAG Functional Timing165PACKAGE INFORMATION166169-Ball CSBGA, 14mm x 14mm (56-G6035-001)166DOCUMENT REVISION HISTORY167Taille: 970 koPages: 167Language: EnglishOuvrir le manuel