Manuel D’UtilisationTable des matièresNI 5401 User Manual1Support2Worldwide Technical Support and Product Information2National Instruments Corporate Headquarters2Worldwide Offices2Important Information3Warranty3Copyright3Trademarks3WARNING REGARDING MEDICAL AND CLINICAL USE OF NATIONAL INSTRUMENTS PRODUCTS3Conventions4Contents5Chapter 1 Generating Functions with the NI 54018About Your NI 54018Connecting Signals9ARB Connector10SYNC Connector10PLL Ref Connector11Pattern Out Connector (PCI Only)12Connector Pin Assignments12Signal Descriptions13SHC50-68 50-Pin Cable Connector13Software Options for Your NI 540115Software Included with Your NI 540115VirtualBench15NI-FGEN Instrument Driver16Additional National Instruments Development Tools16LabVIEW16LabWindows/CVI17ComponentWorks17Using the Soft Front Panels to Generate Waveforms18Generating Standard Functions18Generating Multiple Frequencies in a Sequence20Waveform Editor22Power-Up and Reset Conditions23Chapter 2 Function Generator Operation24Generating Waveforms25Direct Digital Synthesis (DDS)26Frequency Hopping and Sweeping27Triggering27Trigger Sources27Modes of Operation28Single Trigger Mode28Continuous Trigger Mode29Stepped Trigger Mode30Analog Output30SYNC Output and Duty Cycle32Output Attenuation32Output Impedance33Output Enable33Pre-Attenuation Offset34Phase-Locked Loops and Board Synchronization34Analog Filter Correction36RTSI/PXI Trigger Lines37Calibration38Appendix A Specifications39Analog Output39Voltage Output39Triggers41Bus Interface41Operational Modes41SYNC Out42External Clock Reference Input42Internal Clock42Mechanical42Appendix B Optional Accessories43Cabling43Appendix C Frequency Resolution and Lookup Memory44Appendix D Technical Support Resources46NI Web Support46On-Line Problem-Solving and Diagnostic Resources46Software-Related Resources47Worldwide Support47Glossary48Numbers/Symbols48A48B49C49D49E50F51G51H51I52K52L52M53N53O53P53R54S54T55U55V56W56Index57A57B57C57D57E57F57I58L58M58N58O58P58R59S59T59V59W60Figures6Figure 1-1. NI 5401 I/O Connectors9Figure 1-2. Output Levels and Load Termination Using a 50 W Output Impedance10Figure 1-3. SYNC Output and Duty Cycle11Figure 1-4. NI 5401 50-Pin Digital Connector Pin Assignments12Figure 1-5. SHC50-68 68-Pin Connector Pin Assignments14Figure 1-6. VirtualBench-FG Soft Front Panel for Function Generation18Figure 1-7. VirtualBench-FG General Settings Dialog Box for the NI 540119Figure 1-8. VirtualBench-FG Signals Settings Dialog Box for the NI 540119Figure 1-9. VirtualBench-FG Load Waveform Dialog Box20Figure 1-10. VirtualBench-FG Frequency List Editor Dialog Box21Figure 1-11. Waveform Editor Soft Front Panel22Figure 2-1. NI 5401 Block Diagram24Figure 2-2. Waveform Data Path Block Diagram25Figure 2-3. DDS Building Blocks26Figure 2-4. Waveform Generation Trigger Sources28Figure 2-5. Single Trigger Mode29Figure 2-6. Continuous Trigger Mode29Figure 2-7. Stepped Trigger Mode30Figure 2-8. Analog Output and SYNC Out Block Diagram31Figure 2-9. Waveform and Trigger Timings31Figure 2-10. Output Attenuation Chain32Figure 2-11. PLL Architecture for the NI 5401 for PCI35Figure 2-12. PLL Architecture for the NI 5401 for PXI35Figure 2-13. Analog Filter Correction36Figure 2-14. RTSI Trigger Lines and Routing for the NI 5401 for PCI37Figure 2-15. PXI Trigger Lines, 10 MHz Backplane Oscillator, and Routing for the NI 5401 for PXI37Table7Table 1-1. Digital Connector Signal Descriptions13Taille: 480 koPages: 60Language: EnglishOuvrir le manuel