Manuels d'utilisation pour National Instruments NI 5401

Table des matières

• NI 5401 User Manual

  1
• Support

  2
  • Worldwide Technical Support and Product Information

    2
  • National Instruments Corporate Headquarters

    2
  • Worldwide Offices

    2
• Important Information

  3
  • Warranty

    3
  • Copyright

    3
  • Trademarks

    3
  • WARNING REGARDING MEDICAL AND CLINICAL USE OF NATIONAL INSTRUMENTS PRODUCTS

    3
• Conventions

  4
• Contents

  5
• Chapter 1 Generating Functions with the NI 5401

  8
  • About Your NI 5401

    8
  • Connecting Signals

    9
    • ARB Connector

      10
    • SYNC Connector

      10
    • PLL Ref Connector

      11
    • Pattern Out Connector (PCI Only)

      12
      • Connector Pin Assignments

        12
      • Signal Descriptions

        13
    • SHC50-68 50-Pin Cable Connector

      13
  • Software Options for Your NI 5401

    15
    • Software Included with Your NI 5401

      15
      • VirtualBench

        15
      • NI-FGEN Instrument Driver

        16
    • Additional National Instruments Development Tools

      16
      • LabVIEW

        16
      • LabWindows/CVI

        17
      • ComponentWorks

        17
  • Using the Soft Front Panels to Generate Waveforms

    18
    • Generating Standard Functions

      18
    • Generating Multiple Frequencies in a Sequence

      20
    • Waveform Editor

      22
  • Power-Up and Reset Conditions

    23
• Chapter 2 Function Generator Operation

  24
  • Generating Waveforms

    25
  • Direct Digital Synthesis (DDS)

    26
    • Frequency Hopping and Sweeping

      27
  • Triggering

    27
    • Trigger Sources

      27
    • Modes of Operation

      28
      • Single Trigger Mode

        28
      • Continuous Trigger Mode

        29
      • Stepped Trigger Mode

        30
  • Analog Output

    30
    • SYNC Output and Duty Cycle

      32
    • Output Attenuation

      32
    • Output Impedance

      33
    • Output Enable

      33
    • Pre-Attenuation Offset

      34
  • Phase-Locked Loops and Board Synchronization

    34
  • Analog Filter Correction

    36
  • RTSI/PXI Trigger Lines

    37
  • Calibration

    38
• Appendix A Specifications

  39
  • Analog Output

    39
  • Voltage Output

    39
  • Triggers

    41
  • Bus Interface

    41
  • Operational Modes

    41
  • SYNC Out

    42
  • External Clock Reference Input

    42
  • Internal Clock

    42
  • Mechanical

    42
• Appendix B Optional Accessories

  43
  • Cabling

    43
• Appendix C Frequency Resolution and Lookup Memory

  44
• Appendix D Technical Support Resources

  46
  • NI Web Support

    46
    • On-Line Problem-Solving and Diagnostic Resources

      46
    • Software-Related Resources

      47
  • Worldwide Support

    47
• Glossary

  48
  • Numbers/Symbols

    48
  • A

    48
  • B

    49
  • C

    49
  • D

    49
  • E

    50
  • F

    51
  • G

    51
  • H

    51
  • I

    52
  • K

    52
  • L

    52
  • M

    53
  • N

    53
  • O

    53
  • P

    53
  • R

    54
  • S

    54
  • T

    55
  • U

    55
  • V

    56
  • W

    56
• Index

  57
  • A

    57
  • B

    57
  • C

    57
  • D

    57
  • E

    57
  • F

    57
  • I

    58
  • L

    58
  • M

    58
  • N

    58
  • O

    58
  • P

    58
  • R

    59
  • S

    59
  • T

    59
  • V

    59
  • W

    60
• Figures

  6
  • Figure 1-1. NI 5401 I/O Connectors

    9
  • Figure 1-2. Output Levels and Load Termination Using a 50 W Output Impedance

    10
  • Figure 1-3. SYNC Output and Duty Cycle

    11
  • Figure 1-4. NI 5401 50-Pin Digital Connector Pin Assignments

    12
  • Figure 1-5. SHC50-68 68-Pin Connector Pin Assignments

    14
  • Figure 1-6. VirtualBench-FG Soft Front Panel for Function Generation

    18
  • Figure 1-7. VirtualBench-FG General Settings Dialog Box for the NI 5401

    19
  • Figure 1-8. VirtualBench-FG Signals Settings Dialog Box for the NI 5401

    19
  • Figure 1-9. VirtualBench-FG Load Waveform Dialog Box

    20
  • Figure 1-10. VirtualBench-FG Frequency List Editor Dialog Box

    21
  • Figure 1-11. Waveform Editor Soft Front Panel

    22
  • Figure 2-1. NI 5401 Block Diagram

    24
  • Figure 2-2. Waveform Data Path Block Diagram

    25
  • Figure 2-3. DDS Building Blocks

    26
  • Figure 2-4. Waveform Generation Trigger Sources

    28
  • Figure 2-5. Single Trigger Mode

    29
  • Figure 2-6. Continuous Trigger Mode

    29
  • Figure 2-7. Stepped Trigger Mode

    30
  • Figure 2-8. Analog Output and SYNC Out Block Diagram

    31
  • Figure 2-9. Waveform and Trigger Timings

    31
  • Figure 2-10. Output Attenuation Chain

    32
  • Figure 2-11. PLL Architecture for the NI 5401 for PCI

    35
  • Figure 2-12. PLL Architecture for the NI 5401 for PXI

    35
  • Figure 2-13. Analog Filter Correction

    36
  • Figure 2-14. RTSI Trigger Lines and Routing for the NI 5401 for PCI

    37
  • Figure 2-15. PXI Trigger Lines, 10 MHz Backplane Oscillator, and Routing for the NI 5401 for PXI

    37
• Table

  7
  • Table 1-1. Digital Connector Signal Descriptions

    13