Manuels d'utilisation pour Renesas 16-bit single-chip microcomputer

Table des matières

• Keep safety first in your circuit designs!

  2
• Notes regarding these materials

  2
• How to Use This Manual

  3
  • 1. Introduction

    3
  • 2. Register Diagram

    3
  • 3. M16C Family Documents

    4
• Table of Contents

  5
• SFR Page Reference

  11
• 1. Overview

  17
  • 1.1 Applications

    17
  • 1.2 Performance Outline

    18
  • 1.3 Block Diagram

    20
  • 1.4 Product List

    21
  • 1.5 Pin Configuration

    22
  • 1.6 Pin Description

    24
• 2. Central Processing Unit (CPU)

  26
  • 2.1 Data Registers (R0, R1, R2, and R3)

    26
  • 2.2 Address Registers (A0 and A1)

    26
  • 2.3 Frame Base Register (FB)

    27
  • 2.4 Interrupt Table Register (INTB)

    27
  • 2.5 Program Counter (PC)

    27
  • 2.6 User Stack Pointer (USP), Interrupt Stack Pointer (ISP)

    27
  • 2.7 Static Base Register (SB)

    27
  • 2.8 Flag Register (FLG)

    27
    • 2.8.1 Carry Flag (C Flag)

      27
    • 2.8.2 Debug Flag (D Flag)

      27
    • 2.8.3 Zero Flag (Z Flag)

      27
    • 2.8.4 Sign Flag (S Flag)

      27
    • 2.8.5 Register Bank Select Flag (B Flag)

      27
    • 2.8.6 Overflow Flag (O Flag)

      27
    • 2.8.7 Interrupt Enable Flag (I Flag)

      27
    • 2.8.8 Stack Pointer Select Flag (U Flag)

      27
    • 2.8.9 Processor Interrupt Priority Level (IPL)

      27
    • 2.8.10 Reserved Area

      27
• 3. Memory

  28
• 4. Special Function Register (SFR)

  29
• 5. Reset

  41
  • 5.1 Hardware Reset

    41
    • 5.1.1 Reset on a Stable Supply Voltage

      41
    • 5.1.2 Power-on Reset

      41
  • 5.2 Software Reset

    41
  • 5.3 Watchdog Timer Reset

    41
  • 5.4 Oscillation Stop Detection Reset

    41
• 6. Processor Mode

  44
• 7. Clock Generating Circuit

  47
  • 7.1 Types of Clock Generating Circuit

    47
    • 7.1.1 Main Clock

      55
    • 7.1.2 Sub Clock

      56
    • 7.1.3 On-chip Oscillator Clock

      57
    • 7.1.4 PLL Clock

      57
  • 7.2 CPU Clock and Peripheral Function Clock

    59
    • 7.2.1 CPU Clock and BCLK

      59
    • 7.2.2 Peripheral Function Clock

      59
  • 7.3 Clock Output Function

    59
  • 7.4 Power Control

    60
    • 7.4.1 Normal Operation Mode

      60
    • 7.4.2 Wait Mode

      62
    • 7.4.3 Stop Mode

      64
  • 7.5 Oscillation Stop and Re-oscillation Detection Function

    69
    • 7.5.1 Operation When CM27 Bit = 0 (Oscillation Stop Detection Reset)

      69
    • 7.5.2 Operation When CM27 Bit = 1 (Oscillation Stop, Re-oscillation Detection Interrupt)

      69
    • 7.5.3 How to Use Oscillation Stop and Re-oscillation Detection Function

      70
• 8. Protection

  71
• 9. Interrupt

  72
  • 9.1 Type of Interrupts

    72
  • 9.2 Software Interrupts

    73
    • 9.2.1 Undefined Instruction Interrupt

      73
    • 9.2.2 Overflow Interrupt

      73
    • 9.2.3 BRK Interrupt

      73
    • 9.2.4 INT Instruction Interrupt

      73
  • 9.3 Hardware Interrupts

    74
    • 9.3.1 Special Interrupts

      74
    • 9.3.2 Peripheral Function Interrupts

      74
  • 9.4 Interrupts and Interrupt Vector

    75
    • 9.4.1 Fixed Vector Tables

      75
    • 9.4.2 Relocatable Vector Tables

      75
  • 9.5 Interrupt Control

    77
    • 9.5.1 I Flag

      79
    • 9.5.2 IR Bit

      79
    • 9.5.3 ILVL2 to ILVL0 Bits and IPL

      79
    • 9.5.4 Interrupt Sequence

      80
    • 9.5.5 Interrupt Response Time

      81
    • 9.5.6 Variation of IPL when Interrupt Request is Accepted

      81
    • 9.5.7 Saving Registers

      82
    • 9.5.8 Returning from an Interrupt Routine

      83
    • 9.5.9 Interrupt Priority

      83
    • 9.5.10 Interrupt Priority Resolution Circuit

      83
  • 9.6 INT Interrupt

    85
  • 9.7 NMI Interrupt

    89
  • 9.8 Key Input Interrupt

    89
  • 9.9 CAN0 Wake-up Interrupt

    89
  • 9.10 Address Match Interrupt

    90
• 10. Watchdog Timer

  92
  • 10.1 Count Source Protective Mode

    93
• 11. DMAC

  94
  • 11.1 Transfer Cycle

    99
    • 11.1.1 Effect of Source and Destination Addresses

      99
    • 11.1.2 Effect of Software Wait

      99
  • 11.2 DMA Transfer Cycles

    101
  • 11.3 DMA Enable

    102
  • 11.4 DMA Request

    102
  • 11.5 Channel Priority and DMA Transfer Timing

    103
• 12. Timers

  104
  • 12.1 Timer A

    106
    • 12.1.1 Timer Mode

      110
    • 12.1.2 Event Counter Mode

      111
    • 12.1.3 One-shot Timer Mode

      116
    • 12.1.4 Pulse Width Modulation (PWM) Mode

      118
  • 12.2 Timer B

    121
    • 12.2.1 Timer Mode

      124
    • 12.2.2 Event Counter Mode

      125
    • 12.2.3 Pulse Period and Pulse Width Measurement Mode

      126
• 13. Three-Phase Motor Control Timer Function

  129
• 14. Serial I/O

  140
  • 14.1 UARTi

    140
    • 14.1.1 Clock Synchronous Serial I/O Mode

      150
    • 14.1.2 Clock Asynchronous Serial I/O (UART) Mode

      158
    • 14.1.3 Special Mode 1 (I 2 C Mode)

      166
    • 14.1.4 Special Mode 2

      175
    • 14.1.5 Special Mode 3 (IE Mode)

      180
    • 14.1.6 Special Mode 4 (SIM Mode) (UART2)

      182
  • 14.2 SI/Oi

    187
    • 14.2.1 SI/Oi Operation Timing

      191
    • 14.2.2 CLK Polarity Selection

      191
    • 14.2.3 Functions for Setting an SOUTi Initial Value

      192
• 15. A/D Converter

  193
  • 15.1 Mode Description

    197
    • 15.1.1 One-shot Mode

      197
    • 15.1.2 Repeat Mode

      199
    • 15.1.3 Single Sweep Mode

      201
    • 15.1.4 Repeat Sweep Mode 0

      203
    • 15.1.5 Repeat Sweep Mode 1

      205
  • 15.2 Function

    207
    • 15.2.1 Resolution Select Function

      207
    • 15.2.2 Sample and Hold

      207
    • 15.2.3 Extended Analog Input Pins

      207
    • 15.2.4 External Operation Amplifier (Op-Amp) Connection Mode

      207
    • 15.2.5 Current Consumption Reducing Function

      208
    • 15.2.6 Output Impedance of Sensor under A/D Conversion

      208
• 16. D/A Converter

  210
• 17. CRC Calculation

  212
• 18. CAN Module

  214
  • 18.1 CAN Module-Related Registers

    215
    • 18.1.1 CAN Message Box

      215
    • 18.1.2 Acceptance Mask Registers

      215
    • 18.1.3 CAN SFR Registers

      215
  • 18.2 CAN0 Message Box

    216
  • 18.3 Acceptance Mask Registers

    218
  • 18.4 CAN SFR Registers

    219
  • 18.5 Operational Modes

    226
    • 18.5.1 CAN Reset/Initialization Mode

      226
    • 18.5.2 CAN Operation Mode

      227
    • 18.5.3 CAN Sleep Mode

      227
    • 18.5.4 CAN Interface Sleep Mode

      227
    • 18.5.5 Bus Off State

      228
  • 18.6 Configuration CAN Module System Clock

    229
  • 18.7 Bit Timing Configuration

    229
  • 18.8 Bit-rate

    230
  • 18.9 Acceptance Filtering Function and Masking Function

    231
  • 18.10 Acceptance Filter Support Unit (ASU)

    232
  • 18.11 Basic CAN Mode

    233
  • 18.12 Return from Bus off Function

    234
  • 18.13 Time Stamp Counter and Time Stamp Function

    234
  • 18.14 Listen-Only Mode

    234
  • 18.15 Reception and Transmission

    235
    • 18.15.1 Reception

      236
    • 18.15.2 Transmission

      237
  • 18.16 CAN Interrupt

    238
• 19. Programmable I/O Ports

  239
  • 19.1 PDi Register

    240
  • 19.2 Pi Register, PC14 Register

    240
  • 19.3 PURj Register

    240
  • 19.4 PCR Register

    240
• 20. Flash Memory Version

  251
  • 20.1 Memory Map

    253
    • 20.1.1 Boot Mode

      253
  • 20.2 Functions to Prevent Flash Memory from Rewriting

    253
    • 20.2.1 ROM Code Protect Function

      253
    • 20.2.2 ID Code Check Function

      253
  • 20.3 CPU Rewrite Mode

    255
    • 20.3.1 EW0 Mode

      256
    • 20.3.2 EW1 Mode

      256
    • 20.3.3 FMR0, FMR1 Registers

      257
    • 20.3.4 Precautions on CPU Rewrite Mode

      261
    • 20.3.5 Software Commands

      263
    • 20.3.6 Data Protect Function

      268
    • 20.3.7 Status Register (SRD Registser)

      268
    • 20.3.8 Full Status Check

      270
  • 20.4 Standard Serial I/O Mode

    272
    • 20.4.1 ID Code Check Function

      272
    • 20.4.2 Example of Circuit Application in Standard Serial I/O Mode

      276
  • 20.5 Parallel I/O Mode

    277
    • 20.5.1 User ROM and Boot ROM Areas

      277
    • 20.5.2 ROM Code Protect Function

      277
  • 20.6 CAN I/O Mode

    278
    • 20.6.1 ID Code Check Function

      278
    • 20.6.2 Example of Circuit Application in CAN I/O Mode

      281
• 21. Electrical Characteristics

  282
• 22. Usage Precaution

  292
  • 22.1 SFR

    292
  • 22.2 External Clock

    293
  • 22.3 PLL Frequency Synthesizer

    294
  • 22.4 Power Control

    295
  • 22.5 Oscillation Stop, Re-oscillation Detection Function

    297
  • 22.6 Protection

    298
  • 22.7 Interrupt

    299
    • 22.7.1 Reading Address 00000h

      299
    • 22.7.2 Setting SP

      299
    • 22.7.3 NMI Interrupt

      299
    • 22.7.4 Changing Interrupt Generate Factor

      300
    • 22.7.5 INT Interrupt

      300
    • 22.7.6 Rewrite Interrupt Control Register

      301
    • 22.7.7 Watchdog Timer Interrupt

      301
  • 22.8 DMAC

    302
    • 22.8.1 Write to DMAE Bit in DMiCON Register

      302
  • 22.9 Timers

    303
    • 22.9.1 Timer A

      303
    • 22.9.2 Timer B

      307
  • 22.10 Thee-Phase Motor Control Timer Function

    309
  • 22.11 Serial I/O

    310
    • 22.11.1 Clock Synchronous Serial I/O Mode

      310
    • 22.11.2 Special Modes

      311
    • 22.11.3 SI/Oi

      312
  • 22.12 A/D Converter

    313
  • 22.13 CAN Module

    315
    • 22.13.1 Reading C0STR Register

      315
    • 22.13.2 Performing CAN Configuration

      317
    • 22.13.3 Suggestions to Reduce Power Consumption

      318
    • 22.13.4 CAN Transceiver in Boot Mode

      319
  • 22.14 Programmable I/O Ports

    320
  • 22.15 Dedicated Input Pin

    321
  • 22.16 Electrical Characteristic Differences Between Mask ROM and Flash Memory Version Microcomputers

    322
  • 22.17 Mask ROM Version

    323
  • 22.18 Flash Memory Version

    324
    • 22.18.1 Functions to Prevent Flash Memory from Rewriting

      324
    • 22.18.2 Stop Mode

      324
    • 22.18.3 Wait Mode

      324
    • 22.18.4 Low Power Dissipation Mode and On-Chip Oscillator Low Power Dissipation Mode

      324
    • 22.18.5 Writing Command and Data

      324
    • 22.18.6 Program Command

      324
    • 22.18.7 Lock Bit Program Command

      324
    • 22.18.8 Operation Speed

      325
    • 22.18.9 Prohibited Instructions

      325
    • 22.18.10 Interrupt

      325
    • 22.18.11 How to Access

      325
    • 22.18.12 Rewriting in User ROM Area

      325
    • 22.18.13 DMA Transfer

      325
  • 22.19 Flash Memory Programming Using Boot Program

    326
    • 22.19.1 Programming Using Serial I/O Mode

      326
    • 22.19.2 Programming Using CAN I/O Mode

      326
  • 22.20 Noise

    327
• Appendix 1. Package Dimensions

  328
• Register Index

  329
  • A

    329
    • AD0 to AD7

      196
    • ADCON0, ADCON1

      195
      • ADCON0, ADCON1 (One-shot Mode)

        198
      • ADCON0, ADCON1 (Repeat Mode)

        200
      • ADCON0, ADCON1 (Single Sweep Mode)

        202
      • ADCON0, ADCON1 (Repeat Sweep Mode 0)

        204
      • ADCON0, ADCON1 (Repeat Sweep Mode 1)

        206
    • ADCON2

      196
    • ADIC

      77
    • AIER

      91
    • AIER2

      91
  • C

    329
    • C01ERRIC

      77
    • C01WKIC

      77
    • C0AFS

      225
    • C0CONR

      224
    • C0CTLR

      220
    • C0GMR

      218
    • C0ICR

      223
    • C0IDR

      223
    • C0LMAR

      218
    • C0LMBR

      218
    • C0MCTL0 to C0MCTL15

      219
    • C0RECIC

      77
    • C0RECR

      225
    • C0SSTR

      223
    • C0STR

      222
    • C0TECR

      225
    • C0TRMIC

      77
    • C0TSR

      225
    • C1CTLR

      221
    • CAN0 Slot 0 to 15_1

      216
    • CAN0 Slot 0 to 15_2

      217
    • CCLKR

      53
    • CM0

      49
    • CM1

      50
    • CM2

      51
    • CPSRF (Timer A)

      109
    • CPSRF (Timer B)

      123
    • CRCD

      212
    • CRCIN

      212
  • D

    329
    • DA0, DA1

      211
    • DACON

      211
    • DAR0, DAR1

      98
    • DM0CON, DM1CON

      97
    • DM0IC,DM1IC

      77
    • DM0SL

      96
    • DM1SL

      97
    • DTT

      133
  • F

    329
    • FMR0

      257
    • FMR1

      257
  • I

    329
    • ICTB2

      135
    • IDB0, IDB1

      133
    • IFSR0

      86
    • IFSR1

      87
    • IFSR2

      88
    • INT0IC to INT8IC

      78
    • INVC0

      131
    • INVC1

      132
  • K

    329
    • KUPIC

      77
  • O

    329
    • ONSF

      109
  • P

    329
    • P0 to P13

      247
    • PC14

      247
    • PCLKR

      52
    • PCR

      249
    • PD0 to PD13

      246
    • PLC0

      54
    • PM0

      44
    • PM1

      45
    • PM2

      53
    • PRCR

      71
    • PUR0 to PUR2

      248
    • PUR3

      249
  • R

    329
    • RMAD0 to RMAD3

      91
    • ROMCP

      254
  • S

    329
    • S0TIC to S2TIC

      77
    • S0RIC to S2RIC

      77
    • S3456TRR

      189
    • S3BRG to S6BRG

      188
    • S3C to S6C

      188
    • S3IC, S4IC

      78
    • S3TRR to S6TRR

      188
    • S5IC, S6IC

      77
    • SAR0, SAR1

      98
  • T

    329
    • TA0 to TA4

      107
    • TA0IC,TA1IC, TA4IC

      77
    • TA0MR to TA4MR

      107
      • TA0MR to TA4MR (Timer Mode)

        110
      • TA0MR to TA4MR (Event Counter Mode_not using two-phase pulse signal processing)

        112
      • TA2MR to TA4MR (Event Counter Mode_using two-phase pulse signal processing)

        114
      • TA0MR to TA4MR (One-shot Timer Mode)

        117
      • TA0MR to TA4MR (Puslse Width Modulation Mode)

        119
      • TA1MR,TA2MR,TA4MR (Three-Phase Motor Control Timer Function)

        137
    • TA1,TA2,TA4 (Three-Phase Motor Control Timer Function)

      134
    • TA11,TA21,TA41 (Three-Phase Motor Control Timer Function)

      134
    • TA2IC, TA3IC

      78
    • TB0 to TB5

      122
    • TB0MR to TB5MR

      122
      • TB0MR to TB5MR (Timer Mode)

        124
      • TB0MR to TB5MR (Event Counter Mode)

        125
      • TB0MR to TB5MR (Pulse Period / Pulse Width Measurement Mode)

        127
    • TABSR (Timer A)

      108
    • TABSR (Timer B)

      123
    • TABSR (Three-Phase Motor Control Timer Function)

      136
    • TB0IC, TB2IC to TB5IC

      77
    • TB1IC

      78
    • TB2 (Three-Phase Motor Control Timer Function)

      134
    • TB2MR (Three-Phase Motor Control Timer Function)

      137
    • TB2SC

      135
    • TBSR

      123
    • TCR0, TCR1

      98
    • TRGSR (Timer A)

      109
    • TRGSR (Three-Phase Motor Control Timer Function)

      136
  • U

    329
    • U0BCNIC to U2BCNIC

      77
    • U0BRG to U2BRG

      144
    • U0C0 to U2C0

      145
    • U0C1 to U2C1

      146
    • U0MR to U2MR

      145
    • U0RB to U2RB

      144
    • U0SMR to U2SMR

      147
    • U0SMR2 to U2SMR2

      148
    • U0SMR3 to U2SMR3

      148
    • U0SMR4 to U2SMR4

      149
    • U0TB to U2TB

      144
    • UCON

      147
    • UDF

      108
  • W

    330
    • WDC

      93
    • WDTS

      93
• REVISION HISTORY

  331