Manuel D’UtilisationTable des matièresChapter 1 Introduction91.1 General Terms and Conventions91.2 General Description9Figure 1.1 LAN8720/LAN8720i System Block Diagram101.3 Architectural Overview101.3.1 Configuration10Figure 1.2 LAN8720/LAN8720i Architectural Overview11Chapter 2 Pin Configuration122.1 Package Pin-out Diagram and Signal Table12Figure 2.1 LAN8720/LAN8720i 24-QFN Pin Assignments (TOP VIEW)12Table 2.1 LAN8720/LAN8720i 24-PIN QFN Pinout13Chapter 3 Pin Description14Table 3.1 Buffer Types143.1 MAC Interface Signals15Table 3.2 RMII Signals 24-QFN153.2 LED Signals15Table 3.3 LED Signals 24-QFN153.3 Management Signals16Table 3.4 Management Signals 24-QFN163.4 General Signals16Table 3.5 General Signals 24-QFN163.5 10/100 Line Interface Signals17Table 3.6 10/100 Line Interface Signals 24-QFN173.6 Analog Reference17Table 3.7 Analog References 24-QFN173.7 Power Signals17Table 3.8 Power Signals 24-QFN17Chapter 4 Architecture Details184.1 Top Level Functional Architecture18Figure 4.1 100Base-TX Data Path184.2 100Base-TX Transmit184.2.1 100M Transmit Data Across the MII/RMII Interface184.2.2 4B/5B Encoding19Table 4.1 4B/5B Code Table194.2.3 Scrambling204.2.4 NRZI and MLT3 Encoding204.2.5 100M Transmit Driver204.2.6 100M Phase Lock Loop (PLL)21Figure 4.2 Receive Data Path214.3 100Base-TX Receive214.3.1 100M Receive Input214.3.2 Equalizer, Baseline Wander Correction and Clock and Data Recovery214.3.3 NRZI and MLT-3 Decoding224.3.4 Descrambling224.3.5 Alignment224.3.6 5B/4B Decoding224.3.7 Receive Data Valid Signal22Figure 4.3 Relationship Between Received Data and Specific MII Signals234.3.8 Receiver Errors234.3.9 100M Receive Data Across the MII/RMII Interface234.4 10Base-T Transmit234.4.1 10M Transmit Data Across the MII/RMII Interface234.4.2 Manchester Encoding244.4.3 10M Transmit Drivers244.5 10Base-T Receive244.5.1 10M Receive Input and Squelch244.5.2 Manchester Decoding244.5.3 10M Receive Data Across the MII/RMII Interface254.5.4 Jabber Detection254.6 MAC Interface254.6.1 RMII254.7 Reference Clock26Table 4.2 REFCLK Modes264.7.1 REF_CLK In Mode27Figure 4.4 External 50MHz clock sources the REF_CLK274.7.2 REF_CLK OUT Mode27Figure 4.5 LAN8720 sources REF_CLK from a 25MHz crystal28Figure 4.6 LAN8720 Sources REF_CLK from External 25MHz Source294.8 Auto-negotiation294.8.1 Parallel Detection314.8.2 Re-starting Auto-negotiation314.8.3 Disabling Auto-negotiation314.8.4 Half vs. Full Duplex314.9 HP Auto-MDIX Support31Figure 4.7 Direct Cable Connection vs. Cross-over Cable Connection324.10 nINTSEL Strapping and LED Polarity Selection32Table 4.3 LED2/nINTSEL Configuration32Figure 4.8 nINTSEL Strapping on LED2334.11 REGOFF and LED Polarity Selection33Figure 4.9 REGOFF Configuration on LED1334.12 PHY Address Strapping344.13 Variable Voltage I/O344.14 Transceiver Management Control344.14.1 Serial Management Interface (SMI)34Figure 4.10 MDIO Timing and Frame Structure - READ Cycle35Figure 4.11 MDIO Timing and Frame Structure - WRITE Cycle35Chapter 5 SMI Register Mapping36Table 5.1 Control Register: Register 0 (Basic)36Table 5.2 Status Register: Register 1 (Basic)36Table 5.3 PHY ID 1 Register: Register 2 (Extended)36Table 5.4 PHY ID 2 Register: Register 3 (Extended)36Table 5.5 Auto-Negotiation Advertisement: Register 4 (Extended)37Table 5.6 Auto-Negotiation Link Partner Base Page Ability Register: Register 5 (Extended)37Table 5.7 Auto-Negotiation Expansion Register: Register 6 (Extended)37Table 5.8 Register 15 (Extended)37Table 5.9 Silicon Revision Register 16: Vendor-Specific37Table 5.10 Mode Control/ Status Register 17: Vendor-Specific38Table 5.11 Special Modes Register 18: Vendor-Specific38Table 5.12 Register 24: Vendor-Specific38Table 5.13 Register 25: Vendor-Specific38Table 5.14 Symbol Error Counter Register 26: Vendor-Specific38Table 5.15 Special Control/Status Indications Register 27: Vendor-Specific39Table 5.16 Special Internal Testability Control Register 28: Vendor-Specific39Table 5.17 Interrupt Source Flags Register 29: Vendor-Specific39Table 5.18 Interrupt Mask Register 30: Vendor-Specific39Table 5.19 PHY Special Control/Status Register 31: Vendor-Specific39Table 5.20 SMI Register Mapping405.1 SMI Register Format40Table 5.21 Register 0 - Basic Control41Table 5.22 Register 1 - Basic Status41Table 5.23 Register 2 - PHY Identifier 142Table 5.24 Register 3 - PHY Identifier 242Table 5.25 Register 4 - Auto Negotiation Advertisement42Table 5.26 Register 5 - Auto Negotiation Link Partner Ability43Table 5.27 Register 6 - Auto Negotiation Expansion44Table 5.28 Register 16 - Silicon Revision44Table 5.29 Register 17 - Mode Control/Status44Table 5.30 Register 18 - Special Modes45Table 5.31 Register 26 - Symbol Error Counter45Table 5.32 Register 27 - Special Control/Status Indications46Table 5.33 Register 28 - Special Internal Testability Controls46Table 5.34 Register 29 - Interrupt Source Flags46Table 5.35 Register 30 - Interrupt Mask47Table 5.36 Register 31 - PHY Special Control/Status475.2 Interrupt Management485.2.1 Primary Interrupt System48Table 5.37 Interrupt Management Table485.2.2 Alternate Interrupt System49Table 5.38 Alternative Interrupt System Management Table495.3 Miscellaneous Functions495.3.1 Carrier Sense495.3.2 Collision Detect505.3.3 Isolate Mode505.3.4 Link Integrity Test505.3.5 Power-Down modes505.3.6 Reset515.3.7 LED Description515.3.8 Loopback Operation51Figure 5.1 Near-end Loopback Block Diagram52Figure 5.2 Far Loopback Block Diagram52Figure 5.3 Connector Loopback Block Diagram535.3.9 Configuration Signals53Table 5.39 MODE[2:0] Bus54Table 5.40 Pin Names for Mode Bits54Chapter 6 AC Electrical Characteristics556.1 Serial Management Interface (SMI) Timing55Figure 6.1 SMI Timing Diagram55Table 6.1 SMI Timing Values556.2 RMII 10/100Base-TX/RX Timings (50MHz REF_CLK IN)566.2.1 RMII 100Base-T TX/RX Timings (50MHz REF_CLK IN)56Figure 6.2 100M RMII Receive Timing Diagram (50MHz REF_CLK IN)56Table 6.2 100M RMII Receive Timing Values (50MHz REF_CLK IN)56Figure 6.3 100M RMII Transmit Timing Diagram (50MHz REF_CLK IN)57Table 6.3 100M RMII Transmit Timing Values (50MHz REF_CLK IN)576.2.2 RMII 10Base-T TX/RX Timings (50MHz REF_CLK IN)58Figure 6.4 10M RMII Receive Timing Diagram (50MHz REF_CLK IN)58Table 6.4 10M RMII Receive Timing Values (50MHz REF_CLK IN)58Figure 6.5 10M RMII Transmit Timing Diagram (50MHz REF_CLK IN)59Table 6.5 10M RMII Transmit Timing Values (50MHz REF_CLK IN)596.3 RMII 10/100Base-TX/RX Timings (50MHz REF_CLK OUT)606.3.1 RMII 100Base-T TX/RX Timings (50MHz REF_CLK OUT)60Figure 6.6 100M RMII Receive Timing Diagram (50MHz REF_CLK OUT)60Table 6.6 100M RMII Receive Timing Values (50MHz REF_CLK OUT)60Figure 6.7 100M RMII Transmit Timing Diagram (50MHz REF_CLK OUT)61Table 6.7 100M RMII Transmit Timing Values (50MHz REF_CLK OUT)616.3.2 RMII 10Base-T TX/RX Timings (50MHz REF_CLK OUT)62Figure 6.8 10M RMII Receive Timing Diagram (50MHz REF_CLK OUT)62Table 6.8 10M RMII Receive Timing Values (50MHz REF_CLK OUT)62Figure 6.9 10M RMII Transmit Timing Diagram (50MHz REF_CLK OUT)63Table 6.9 10M RMII Transmit Timing Values (50MHz REF_CLK OUT)636.4 RMII CLKIN Requirements63Table 6.10 RMII CLKIN (REF_CLK) Timing Values636.5 Reset Timing64Figure 6.10 Reset Timing Diagram64Table 6.11 Reset Timing Values646.6 Clock Circuit65Table 6.12 LAN8720/LAN8720i Crystal Specifications65Chapter 7 DC Electrical Characteristics667.1 DC Characteristics667.1.1 Maximum Guaranteed Ratings66Table 7.1 Maximum Conditions66Table 7.2 ESD and LATCH-UP Performance667.1.2 Operating Conditions67Table 7.3 Recommended Operating Conditions677.1.3 Power Consumption67Table 7.4 Power Consumption Device Only (REF_CLK IN MODE)68Table 7.5 Power Consumption Device Only (50MHz REF_CLK OUT MODE)687.1.4 DC Characteristics - Input and Output Buffers70Table 7.6 RMII Bus Interface Signals70Table 7.7 LAN Interface Signals71Table 7.8 LED Signals71Table 7.9 Configuration Inputs71Table 7.10 General Signals71Table 7.11 Internal Pull-Up / Pull-Down Configurations71Table 7.12 100Base-TX Transceiver Characteristics72Table 7.13 10BASE-T Transceiver Characteristics72Chapter 8 Application Notes738.1 Application Diagram738.1.1 RMII Diagram73Figure 8.1 Simplified Application Diagram738.1.2 Power Supply Diagram74Figure 8.3 High-Level System Diagram for Power748.1.3 Twisted-Pair Interface Diagram74Figure 8.5 Copper Interface Diagram748.2 Magnetics Selection75Chapter 9 Package Outline76Figure 9.1 LAN8720/LAN8720i-EZK 24-QFN Package Outline, 4 x 4 x 0.9 mm Body (Lead-Free)76Table 9.1 24 Terminal QFN Package Parameters76Figure 9.1 QFN, 4x4 Taping Dimensions and Part Orientation77Figure 9.2 Reel Dimensions78Chapter 10 Revision History79Table 10.1 Customer Revision History79Taille: 1,4 MoPages: 79Language: EnglishOuvrir le manuel