Manuels d'utilisation pour STMicroelectronics EVAL BOARD FOR L6563 EVL6563H-250W

Table des matières

• Figure 1. Block diagram

  1
• 1 Description

  6
• 2 Maximum ratings

  7
  • 2.1 Absolute maximum ratings

    7
    • Table 1. Absolute maximum ratings

      7
  • 2.2 Thermal data

    7
    • Table 2. Thermal data

      7
• 3 Pin connection

  8
  • Figure 2. Pin connection

    8
  • Table 3. Pin description

    8
  • Figure 3. Typical system block diagram

    10
• 4 Electrical characteristics

  11
  • Table 4. Electrical characteristics

    11
• 5 Typical electrical performance

  15
  • Figure 4. IC consumption vs VCC

    15
  • Figure 5. IC consumption vs TJ

    15
  • Figure 6. Vcc Zener voltage vs TJ

    15
  • Figure 7. Start-up and UVLO vs TJ

    15
  • Figure 8. Feedback reference vs TJ

    16
  • Figure 9. E/A output clamp levels vs TJ

    16
  • Figure 10. UVLO saturation vs TJ

    16
  • Figure 11. OVP levels vs TJ

    16
  • Figure 12. Inductor saturation threshold vs TJ

    17
  • Figure 13. Vcs clamp vs TJ

    17
  • Figure 14. ZCD sink/source capability vs TJ

    17
  • Figure 15. ZCD clamp level vs TJ

    17
  • Figure 16. TBO clamp vs TJ

    18
  • Figure 17. VVFF - VTBO dropout vs TJ

    18
  • Figure 18. IINV - ITBO current mismatch vs TJ

    18
  • Figure 19. IINV - ITBO mismatch vs ITBO current

    18
  • Figure 20. R discharge vs TJ

    19
  • Figure 21. Line drop detection threshold vs TJ

    19
  • Figure 22. VMULTpk - VVFF dropout vs TJ

    19
  • Figure 23. PFC_OK threshold vs TJ

    19
  • Figure 24. PFC_OK FFD threshold vs TJ

    20
  • Figure 25. PWM_LATCH high saturation vs TJ

    20
  • Figure 26. RUN threshold vs TJ

    20
  • Figure 27. PWM_STOP low saturation vs TJ

    20
  • Figure 28. Multiplier characteristics @ VFF = 1 V

    21
  • Figure 29. Multiplier characteristics @ VFF = 3 V

    21
  • Figure 30. Multiplier gain vs TJ

    21
  • Figure 31. Gate drive clamp vs TJ

    21
  • Figure 32. Gate drive output saturation vs TJ

    22
  • Figure 33. Delay to output vs TJ

    22
  • Figure 34. Start-up timer period vs TJ

    22
  • Figure 35. HV start voltage vs TJ

    22
  • Figure 36. VCC restart voltage vs TJ

    23
  • Figure 37. HV breakdown voltage vs TJ

    23
• 6 Application information

  24
  • 6.1 Overvoltage protection

    24
    • Figure 38. Output voltage setting, OVP and FFP functions: internal block diagram

      24
  • 6.2 Feedback failure protection (FFP)

    25
  • 6.3 Voltage feedforward

    25
    • Figure 39. Voltage feedforward: squarer-divider (1/V2) block diagram and transfer characteristic

      26
    • Figure 40. RFF·CFF as a function of 3rd harmonic distortion introduced in the input current

      27
  • 6.4 THD optimizer circuit

    28
    • Figure 41. THD optimizer circuit

      28
    • Figure 42. THD optimization: standard TM PFC controller (left side) and L6563H (right side)

      29
  • 6.5 Tracking boost function

    29
    • Figure 43. Tracking boost block

      31
    • Figure 44. Tracking output voltage vs Input voltage characteristic with TBO

      31
  • 6.6 Inductor saturation detection

    31
    • Figure 45. Effect of boost inductor saturation on the MOSFET current and detection method

      32
  • 6.7 Power management/housekeeping functions

    32
    • Figure 46. Interface circuits that let dc-dc converter's controller IC drive L6563H in burst mode

      33
    • Figure 47. Interface circuits that let the L6563H switch on or off a PWM controller

      33
    • Figure 48. Interface circuits for power up sequencing when dc-dc has the SS function

      34
    • Figure 49. Interface circuits for actual power-up sequencing (master PFC)

      34
    • Figure 50. Brownout protection (master PFC)

      35
  • 6.8 High-voltage start-up generator

    35
    • Figure 51. High-voltage start-up generator: internal schematic

      35
    • Figure 52. Timing diagram: normal power-up and power-down sequences

      36
    • Figure 53. High-voltage start-up behaviour during latch-off protection

      37
    • Figure 54. High-voltage start-up managing the dc-dc output short-circuit

      37
    • Table 5. Summary of L6563H idle states

      38
• 7 Application examples and ideas

  39
  • Figure 55. Demonstration board EVL6563H-100W, wide-range mains: electrical schematic

    39
  • Figure 56. L6563H 100 W TM PFC evaluation board: compliance to EN61000-3-2 standard

    40
  • Figure 57. L6563H 100 W TM PFC evaluation board: compliance to JEITA-MITI standard

    40
  • Figure 58. L6563H 100 W TM PFC evaluation board: input current waveform @230-50 Hz - 100 W load

    40
  • Figure 59. L6563H 100W TM PFC evaluation board: input current waveform @100 V-50 Hz - 100 W load

    40
  • Figure 60. EVL90WADP-LLCSR 90W adapter with SRK2000 demonstration board: electrical schematic

    41
  • Figure 61. EV150WAIO-LLCSR 150W-12V Adapter with L6563H, L6599A, SRK2000: electrical schematic

    42
  • Figure 62. EVL6563H -250W TM PFC demonstration board: electrical schematic

    43
  • Figure 63. EVL6599A-90WADP 90W Adapter demonstration board: electrical schematic

    44
• 8 Package mechanical data

  45
  • Table 6. SO16 mechanical data

    45
  • Figure 64. SO16 mechanical data

    46
• 9 Ordering codes

  47
  • Table 7. Ordering information

    47
• 10 Revision history

  48
  • Table 8. Document revision history

    48