Manuel D’UtilisationTable des matièresIndustry and Product Overview8System Generator9System Level Modeling with System Generator9The System Generator Design Flow10Arithmetic Data Types12Hardware Handshaking13Multirate Systems13Bit-True and Cycle-True Modeling14Automatic Testbench Generation14What is a Xilinx Block?15Instantiating Xilinx Blocks within a Simulink Model16The Block Parameters Dialog Box16The Nature of Signals in the Xilinx Blockset16Use of Xilinx Smart-IP Cores by the System Generator18Licensed Cores18Xilinx LogiCORE Versions19Common Options in Block Parameters Dialog Box19Arithmetic Type20Implement with Xilinx Smart-IP Core (if possible)20Generate Core20Latency20Precision21Number of Bits21Overflow and Quantization21Override with Doubles21Sample Period22Basic Elements23System Generator23Addressable Shift Register26Black Box28Concat30Constant31Convert31Counter32Delay35Down Sample36Get Valid Bit37Mux38Parallel to Serial39Register40Reinterpret42Serial to Parallel43Set Valid Bit45Slice45Sync47Up Sample50Communication52Convolutional Encoder52Depuncture54Interleaver Deinterleaver55Puncture58RS Decoder59RS Encoder63Viterbi Decoder68DSP70CIC70DDS73FFT75FIR79Math81Accumulator81AddSub83CMult84Inverter85Logical86Mult88Negate90Relational90Scale92Shift92SineCosine93Threshold95MATLAB I/O96Gateway Blocks96Enabled Subsystems96Gateway In97Gateway Out99Quantization Error Blocks101Display101Memory102Dual Port RAM102FIFO106ROM107Single Port RAM110State Machine114Mealy State Machine114Moore State Machine116Registered Mealy State Machine119Registered Moore State Machine123Using the System Generator installer127Uninstalling previous System Generator directories127Installed System Generator directory128Using Black Boxes128Example model128Black Box window129Use of mixed language projects130Incorporating mixed language black boxes130Tips for creating a high performance design132Using the System Generator Constraints Files133System Clock Period133Multicycle Path Constraints133IOB Timing and Placement Constraints134Example for showing constraints use134Important Issues136Files automatically created by System Generator137Xilinx ISE 4.1i Project Navigator139Opening a System Generator project139Customizing your System Generator project139Implementing your design140Simulating using ModelSim within the Project Navigator141Using an EDIF software flow143Simulation143Compiling your IP143Associating ModelSim with ISE 4.1i Project Navigator144Xilinx software tools resources145Demonstration designs146Perl scripts147Taille: 1,4 MoPages: 148Language: EnglishOuvrir le manuel
