Intel 82801EB Manuale Utente
Intel® ICH5 AC ’97 Controller Theory of Operation
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AC ’97 Programmer’s Reference Manual 17
3 Intel
®
ICH5 AC ’97 Controller
Theory of Operation
The ICH5 AC ’97 digital controller (DC) interface is an implementation of the AC-link, with
additional features to support the transaction and device power management. The ICH5 AC’97 DC
includes DMA engines for high-performance data transfer to memory via a hub interface.
additional features to support the transaction and device power management. The ICH5 AC’97 DC
includes DMA engines for high-performance data transfer to memory via a hub interface.
ICH5 AC’97 DC and AC-link support isochronous traffic, which emphasizes the timing of the
data. This is critical to maintain the data stream from the audio and/or modem codec.
data. This is critical to maintain the data stream from the audio and/or modem codec.
3.1 Intel
®
ICH5 AC ’97 Initialization
3.1.1 System
Reset
The ICH5 AC ’97 circuitry is reset on power up by combining the PCIRST# signal with the AC
Link RESET# signal. However, AC Link RESET# will not follow PCIRST# during a resume from
sleep condition. During operation, the system can be reset by clearing the AC ’97 cold reset bit in
the Global Control/Status register (GLOB_CNT). This bit is maintained during ICH5 sleep mode
and can be used by the driver to select warm or cold reset during a resume condition. At least one
codec must be present. Otherwise, ICH5 AC ’97 is not supported and the codec ready will never
be seen by the controller. Once the reset has occurred, a read to Mixer register 00h/80h will
indicate what type of hardware resides in the codec(s).
Link RESET# signal. However, AC Link RESET# will not follow PCIRST# during a resume from
sleep condition. During operation, the system can be reset by clearing the AC ’97 cold reset bit in
the Global Control/Status register (GLOB_CNT). This bit is maintained during ICH5 sleep mode
and can be used by the driver to select warm or cold reset during a resume condition. At least one
codec must be present. Otherwise, ICH5 AC ’97 is not supported and the codec ready will never
be seen by the controller. Once the reset has occurred, a read to Mixer register 00h/80h will
indicate what type of hardware resides in the codec(s).
Software must ensure that the codec ready bit is present for the appropriate Global Control/Status
register (GLOB_CNT). Before writing any value on the codec registers or initiating a DMA
transfer, s/w must ensure that the codec has reached a ready status by reading the Audio codec
register Powerdown Control/Status register (Index 26h) or Extended Modem Status and Control
register (Index 3Eh) correspondingly.
register (GLOB_CNT). Before writing any value on the codec registers or initiating a DMA
transfer, s/w must ensure that the codec has reached a ready status by reading the Audio codec
register Powerdown Control/Status register (Index 26h) or Extended Modem Status and Control
register (Index 3Eh) correspondingly.
3.1.2 Codec
Topology
The following rules present the allowable codec configuration when attaching to the AC-link
interface. To avoid improper driver loading, the system BIOS should determine the presence of the
audio or modem codec attached on the AC-link, and enable the Audio or Modem function’s PCI
configuration space accordingly.
interface. To avoid improper driver loading, the system BIOS should determine the presence of the
audio or modem codec attached on the AC-link, and enable the Audio or Modem function’s PCI
configuration space accordingly.
The following are the loading rules for ICH5:
1. Maximum of three codecs total on the link
2. Maximum of a single modem function, either as Modem Codec or a combination
1. Maximum of three codecs total on the link
2. Maximum of a single modem function, either as Modem Codec or a combination
Audio/Modem Codec
This information is used to disable (hide) the appropriate PCI function. To determine that a codec
or codecs are attached to the link, the System BIOS follows an algorithmic approach.
or codecs are attached to the link, the System BIOS follows an algorithmic approach.