Intel 82801EB Manuale Utente
Intel® ICH5 AC ’97 Controller Theory of Operation
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AC ’97 Programmer’s Reference Manual 23
Table 10. Modem Last Valid Index
Modem Last Valid Index (LVI)
I/O Address:
Line IN
MBAR + 05h (MILVI)
Line OUT
MBAR + 15h (MOLVI),
5. After LVI registers are updated, software sets the run bit in the control register to execute the
descriptor list.
3.2.3
DMA Steady State Operation
Software has two concurrent activities to perform while in normal operation: Preparing new
buffers/buffer descriptors and marking processed buffer descriptors and buffers as free. Once the
run bit is set in the bus master control register bit 0, the bus master fetches the buffer descriptor.
1. Bus master starts processing the current buffer. Once current buffer is processed, depending
buffers/buffer descriptors and marking processed buffer descriptors and buffers as free. Once the
run bit is set in the bus master control register bit 0, the bus master fetches the buffer descriptor.
1. Bus master starts processing the current buffer. Once current buffer is processed, depending
upon the bits set in the command field, the interrupt is asserted and the interrupt bit is set.
2. Bus master increments the current and pre-fetch indices. It then starts executing the current
buffer and schedules the next buffer to be pre-fetched.
3. Buffer service routine maintains a variable that points to the head of the list of descriptors to
be processed. The descriptor list service routine performs the following activities:
// Update head of descriptors to be processed
While (head != current_index)
{
Mark head free ;
// check for end of descriptor list
If head == base_address + (31 * 8);
// last entry on the list, set head to top of the list
head = base_address;
Else
// still inside the list, increment head to next entry
head++;
Caution: This algorithm needs to be optimized to reduce the number of memory accesses during
execution. The “while” statement could translate to several memory access if this code is not
execute after each buffer descriptor update.
execute after each buffer descriptor update.
Also, the routine that prepares buffers maintains a variable that points to the entry after the tail of
the list. This value is always the next entry after the Last Valid Index register. It follows the
following algorithm:
// Update tail of descriptor list ready for execution and audio
// buffers when available for processing
While ((tail == free) && (buffers_available > 0))
{
Prepare buffer descriptor indexed by tail;
buffers_available--;
//assign tail to Last Valid Index
LVI = Tail;
// check for end of descriptor list
If (tail == base_address + 31 * 8);
// last entry on the list, set tail to top of the list
tail = base_address;
Else
the list. This value is always the next entry after the Last Valid Index register. It follows the
following algorithm:
// Update tail of descriptor list ready for execution and audio
// buffers when available for processing
While ((tail == free) && (buffers_available > 0))
{
Prepare buffer descriptor indexed by tail;
buffers_available--;
//assign tail to Last Valid Index
LVI = Tail;
// check for end of descriptor list
If (tail == base_address + 31 * 8);
// last entry on the list, set tail to top of the list
tail = base_address;
Else